Do Core i7s have a Phenom-like TLB issue? No, says Intel

While browsing news sites today, we came upon several reports saying Core i7 processors suffer from a translation lookaside buffer-related erratum. Those reports drew parallels between the TLB bug that plagued AMD’s first quad-core CPUs and a note in Intel’s Core i7 specification update, which states in part:

In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue.

We asked Intel PR manager Dan Snyder for the chipmaker’s official take on the issue, and he replied with the following:

This is simply a pointer to a previous document written in April 2007. This document is an application note (advises on programming techniques) that programmers have had since April of 2007. This item in the Nehalem spec sheet is a web pointer, under the heading "spec clarification". The reporter who wrote this did not contact us and we will try to clarify this with him.

In other words, Intel shareholders probably shouldn’t be losing any sleep over this.

For reference, the AMD TLB erratum caused data corruption and system hangs in periods of high CPU utilization, and AMD halted shipments of quad-core Opterons for months because of it. On the desktop, the company released a BIOS fix that crippled the performance of early quad-core Phenoms in many apps. All Phenoms with model numbers ending in "50" and all shipping quad-core Opterons lack the erratum, though.

Update: Snyder has sent us a new statement that makes the situation even clearer:

The "AAJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS" document is a SPEC CLARIFICATION, and is simply a pointer to a previous document written in April 2007.

SPEC CLARIFICATION AAJ1 was initially added due to an issue on the Intel® Core 2 Duo processor which was previously corrected with a BIOS update; this issue does not impact the Nehalem Family of CPUs. There are errata on the Intel® Core i7 processor that relate to the TLB. These all relate to improper translations or error reporting, and all of those that impact functionality have been fixed via BIOS updates prior to Core i7 launch.

(The emphasis is Intel’s.)

Comments closed
    • blubje
    • 11 years ago

    Who let the AMD fanboys out of their cage?

    A loser named Pluscard is linking to this over on the Yahoo! AMD message board.

    I feel sorry for Pluscard. He was buying more and more AMD as the share price increased to 42. He called the bottom every .25 as it dropped, including buying more shares on MARGIN at almost 7! The margin calls wiped him out, and sometimes he will even admit to losing all his AMD on margin calls.

    He said Intel Core 2 Duo demos were faked by Intel, that shipping silicon would never have that kind of performance. He pretends AMD is “cash flow positive” when they lose billions, he pretends that AMD’s billions in ATI writedowns are meaningless.

    He believed AMD’s promise of Phenom having 40% better performance hook, line and sinker. He also made excuses for AMD SIMULATED PHENOM BENCHMARKS of 2.8 and 3Ghz chips. He said Intel going to 45nm was a mistake and AMD would be wise to not follow. He said Intel’s hafnium transistor breakthrough was nothing of any iimportance.

    The guy is a total IDIOT and should be shunned by all.

    If you value your portfolio, listen to Pluscard, then do the opposite. The harder Pluscard pumps AMD, the more you should short.

      • pluscard
      • 11 years ago

      Sanity check: How would anyone know what trades I make?

      Consider the rest of bubje’s post in that light.

        • green
        • 11 years ago

        it’s not too hard when you’re nick leaves a trail a mile long
        for instancing googling:

        “site:messages.finance.yahoo.com pluscard bought”

        brought up this one:
        §[<http://messages.finance.yahoo.com/Stocks_(A_to_Z)/Stocks_A/threadview?m=tm&bn=893&tid=1652211&mid=1652307&tof=56&rt=1&frt=2&off=1<]§ so there are at least trails around indicating you're buying amd unless of course you're lying about what trades you make

          • pluscard
          • 11 years ago

          Of course I own AMD shares – i think I’ve posted that here before. In Jan’08 when I posted I made two buys, the shareprice was $6. The guy I was refuting says I bought in the $40’s which I did not.

          Messages board bashers always claim longs bought at the extreme highs, then “calculate” losses. My point is most of what they post is BS, and claiming I bought in the $40’s was easy to refute. Giving the license he takes regarding my buys, you can decide how much weight to put on the balance of his flame.

          His post serves to prove my premise – who takes the time to research an ID, then goes to another board to discredit their posts?

          Plus

    • sdack
    • 11 years ago

    The old, slow paper press had several advantages:

    1) It was great for swatting flies.

    2) One could wrap fish in it.

    3) There was always a chance for a rumor not to go into an edition, because a press was already running, and if over night the rumor died off then nobody would ever know about it.

    • brucect
    • 11 years ago

    Where is all the bug articles 25 page coverage ? Will it come?

      • eitje
      • 11 years ago

      Welcome to Tech Report!

      • crazybus
      • 11 years ago

      Which of the published errata do you think deserves a 25 page article? Or are you just trolling?

        • brucect
        • 11 years ago

        i have been reading TR long time . they are pretty good on objective news
        i meant some other sites like tom’s or anand s when amd s tlb they have many articles but intel tlb they did not even put on news section.shame

    • poulpy
    • 11 years ago

    /[<"For reference, the AMD TLB erratum caused data corruption and system hangs in periods of high CPU utilization, and AMD halted shipments of quad-core Opterons for months because of it."<]/ AFAIK for reference the Phenom bug was only reproducible in periods of high CPU utilization *[

    • bogbox
    • 11 years ago

    This is the diffrence between Intel and AMD : Intel PR is much better than AMD PR.
    Even if there is a problem Intel will never say is a problem, nor change the name to include a “fix”, like AMD.
    Intel will send to MS the problem specification and fix. as well to motherboard makers the bios fix.

    But the consumers not need to know about it.

    • Fighterpilot
    • 11 years ago

    I love it when Jumpin Jack pops in and lays a badass answer on someone.
    Always the facts and good info…nice one Jack.

    • Auril4
    • 11 years ago

    Just remember, when a site like this is heavily sponsored by a manufacturer such as Intel, there is a good chance that the objectivity of an article like this will be ‘slightly’ skewed.
    It might even be ‘Intel approved’

      • DaveJB
      • 11 years ago

      Tell me, have you ever heard of the phrase “Appeal to Motive?” Because saying “TR is taking money from Intel, therefore anything they say with regard to Intel is wrong/skewed/biased” isn’t a logical argument; in fact, it’s a logical /[

        • Spotpuff
        • 11 years ago

        In my experience trying to get people to admit they are wrong by demonstrating their logical fallacies is about as effective as ice skating up hill.

        • ish718
        • 11 years ago

        Key words *good chance*.

        Now be gone, logic man.

      • MadManOriginal
      • 11 years ago

      I wasn’t aware TR was sponsored by Intel. They get hardware to test which they may have to return. That is the case with all (? probably) the gear they test. In which case, by your logic, none of the results on this site nor any other hardware site are unskewed.

      Better call Scully!

      • sdack
      • 11 years ago

      I am not sure if you are talking about TR because TR does not seem to lean to Intel for other reasons than Intel’s products. If you are saying the article reads smoky then I do have to agree.

      The funniest sentence probably is:

      /[<"Intel shareholders probably shouldn't be losing any sleep over this."<]/

        • pluscard
        • 11 years ago

        After reading all the spin and shift to a 2007 core2 issue, you have to put on reading glasses to see this intel quote: “There are errata on the Intel® Core i7 processor that relate to the TLB…”

        Does that end the discussion?

          • sdack
          • 11 years ago

          I do not think so.

          • jasonalwaysready
          • 11 years ago

          l[<"There are errata on the Intel® Core i7 processor that relate to the TLB..."<]l "...and all of those that impact functionality have been fixed via BIOS updates prior to Core i7 launch."

      • SomeOtherGeek
      • 11 years ago

      LOL!! You are kidding right?? If not, then that is probably the dumbest dumb question or comment I have heard of late!

    • Forge
    • 11 years ago

    No, three years ago and change Intel explained the penalties involved in breaking my three year term NDA.

    Telling you that the Prescott was a stinking dog, and my P4 560 3.6GHz Preshott benched out lower than my 2.8C Northwood in many cases would result in immediate and improper usage of the following:

    Blowtorch
    3 pair Pliers
    1 Ball peen hammer
    1 Deadblow hammer
    6 2×4″ pieces of pressure treated lumber
    1 propane blowtorch
    1 medieval ‘pear’

    and optionally, at the discretion of the Intel rep;

    THE BRAZEN BULL.

    Edit: When I started typing this would have been #3. It’s in reply to #1.

      • OneArmedScissor
      • 11 years ago

      BALL PEEN HAMMER!

    • Pachyuromys
    • 11 years ago

    Three things come to mind:
    1) In his initial reply, PR Manager (/[

      • UberGerbil
      • 11 years ago

      Actually, if you’ve been following this since the last time there was an Intel TLB controversy, back in 2007 with Core 2, both the clarification and the reference to the previous document makes sense. Or you could follow the link in this article, which takes you to the “Intel® Core™ i7 Processor Extreme Edition Series and Intel® Core™ i7 Processor Specification Update November 2008” PDF, on page 37 of which (“AAJ1. Clarification of TRANSLATION LOOKASIDE BUFFERS”) is a link to said previous document, which can be found at §[<http://www.intel.com/products/processor/manuals/index.htm<]§ ("Intel® 64 and IA-32 Architectures Application Note: TLBs, Paging-Structure Caches, and Their Invalidation") which AFAICT hasn't been revised since April 2008. In other words, this issue looks no different from the one in Core 2, and any fixes for that (eg §[<http://support.microsoft.com/kb/936357<]§ ) would apply here too. With the Core 2 there was no performance hit with the fix, and the problem itself wasn't so much a bug as a part of the architecture that had never been fully specified. Intel decided to change something that happened to conflict with the way some OSes expected things to work, so we had a conflict with what amounted to a de facto spec. Intel responded with a de jure spec (the "clarification") and the OSes got patched. And the BIOSes for the i7 presumably would've picked this up as well. So from the looks of it this was fixed before the i7 even existed in its final form.

      • Damage
      • 11 years ago

      This particular spin doctor has a pair of engineering degrees from renowned schools. You might want to check your assumptions here. He’s giving us an on-the-record denial that there’s a substantial problem in his official capacity as an Intel spokesman. We will, of course, monitor the issue, but this is credible information we judged worthy of relaying to our readers.

        • Pachyuromys
        • 11 years ago

        Pffft, that doesn’t necessarily mean squat. My brother has an engineering degree from the Colorado School of Mines, one of the most prestigious geology and petroleum engineering schools in the world, but on the way to being promoted to Chief Operating Officer of his pipeline company he hasn’t actually /[

          • mako
          • 11 years ago

          And your qualifications are…?

            • Pachyuromys
            • 11 years ago

            …are no better or worse than any individual that uses critical thinking to question the veracity of any statement made by any public relations department or firm. PR is just institutionalized lying that social complacency has made acceptable and even *cough* respectable, a la Damage’s defense.

          • d2brothe
          • 11 years ago

          The individuals who actually worked on the chip aren`t qualified to speak to reporters. Thats not their job, and they`re generally very bad at it. Thats why you have a PR person.

            • w00tstock
            • 11 years ago

            Well-well look. I already told you: I deal with the god damn customers so the engineers don’t have to. I have people skills; I am good at dealing with people. Can’t you understand that? What the hell is wrong with you people?

          • MadManOriginal
          • 11 years ago

          So if it was hand-fed to him by ‘real’ engineers doesn’t that make the information valid?

      • crazybus
      • 11 years ago

      I’m not sure if you even bothered to look at the Core i7 spec update, but if you did, you must have missed the fact that this “bug” is not even referenced in the list of errata. A minimal amount of follow up would indicate that this was a (fixed) Core 2 issue. If it even still exists in Nehalem one would logically assume it is fixed there as well.

      If you’ve ever looked at Intel processor documentation, you’ll notice they do a lot of copy-and-paste between documents, which leads to misleading information in some cases.

      If you want to make an issue of errata that /[

      • JumpingJack
      • 11 years ago

      Point 1.
      “Snyder only refers to some “previous document. Three times, in fact”

      Here is the Core i7 spec update: §[<http://download.intel.com/design/processor/specupdt/320836.pdf<]§ (page 37) Here is the Core 2 Duo udpate: §[<http://download.intel.com/design/processor/specupdt/313279.pdf<]§ (page 71) This is what he refers to 3 times. Here is the initial news of the Core 2 Duo update to address any problems the OS may have managing the translation lookaside buffers and the MS update: §[<http://support.microsoft.com/kb/936357<]§ §[<http://www.theinquirer.net/en/inquirer/news/2007/06/26/critical-update-for-intel-core-cpus-is-out<]§ Of course, the press sensationalized this information as 'critical' when it is nothing more than code to address specifics to a new processors memory handling hardware. Point 2. There is no bug in this context, this is a documentation clarification in terms of how to invlidate a page tracked in the TLB. At last recollection, clarification is a means by which a something is made more clear, to free from obscurity or ambiguity. This not the same as an errata, which is why it occurs under the section called "Specification Clarification" and not in the "Errata Section". Quoting from the spec update: "Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly." TLBs are specialized, very fast caches that contain no data or instructions, just pointers. Their job is to store and translate page tables for virtual memory addresses to physical memory addresses. This is a hardware feature of memory management that all processors provide to the OS, but it is the OS that is ultimately responsible for ensuring proper memory management (the overhead is too much to handle completely in hardware). In order for the OS kernel to do the job correctly, programmers must know all the details of how the cache tables, TLBs, and memory management hardware of the processor functions otherwise strange things will happen. Point 3. Your point is pointless. Jack

        • Pachyuromys
        • 11 years ago

        Now see, if the PR guy had said /[

          • SomeOtherGeek
          • 11 years ago

          In that case, you pick the case, I’ll just stick with the Core 2. Thank you very much!

          • SPOOFE
          • 11 years ago

          “Now see, if the PR guy had said that… end of discussion.”

          He probably didn’t realize he was having a discussion with you.

    • Anomymous Gerbil
    • 11 years ago

    How do BIOS settings fix issues deep within the CPU like that?

      • Meadows
      • 11 years ago

      They tell the processor to execute a given instruction in a slightly different (and probably slower) way, or substitute said instruction with a group of different ones (even slower).

      • Perezoso
      • 11 years ago

      by loading microcode patches and/or changing some settings

      • ludi
      • 11 years ago

      Most modern CPUs have the ability to load a small amount of machine code that will intercept and modify how certain processing operations are handled. Inasmuch as it is virtually impossible to build a modern processor with no bugs whatsoever, microcode updates are a popular workaround for minor errata. A common way of implementing a microcode update is to have the BIOS load it into the CPU at boot-up, where it will then stay until power is lost.

        • UberGerbil
        • 11 years ago

        Fun trivia: in the old days on some systems you were able to load microcode at boot from a floppy. We had Xerox workstations (with the original “GUI” — you know, the one that Apple stole) that could boot as regular PARC (Alto) workstations, or they could load microcode to boot as hardware LISP machines. LISP machines. Running Unix.

        Yeah, loading microcode from a floppy — an 8″ floppy! — was not quick. Then there was all the network initialization (these things were on ethernet, with a laser printer and distributed storage — all very slick for the 80s).

        You think it takes too long for machines to boot today…

          • ClickClick5
          • 11 years ago

          “Hot dang Jim, we lost power again! Get the punch-cards out…we gonna be here a while! Wind up the hard drive while your at it.”

          lol

            • sroylance
            • 11 years ago

            You toggle in the boot loader while I get the OS tape spooled up

        • Anomymous Gerbil
        • 11 years ago

        Cheers.

    • crazybus
    • 11 years ago

    Wow, the the journalistic and technical incompetence displayed at Fudzilla reminds me why I don’t go there.

      • Ardrid
      • 11 years ago

      It’s Fudo from the Inq. Did we really expect anything more from such a fanboy putz?

    • ludi
    • 11 years ago

    mis-post. Whoops.

    • Mr Bill
    • 11 years ago

    Stirring, I know. But wasn’t the Phenom TLB problem also taken care of with a bios fix?

      • crazybus
      • 11 years ago

      I don’t know if you could call the massive memory subsytem performance hit a “fix”. I think the cure was worse than the disease, considering how unlikely you were to encounter issues in the desktop environment.

      • clhensle
      • 11 years ago

      The fix was to turn off the some of the cache, kinda like removing a lung if you have a cough, most people disabled the “fix” because they were fine with the tiny chance of a program crash, over losing 13-20% performance.

      §[<https://techreport.com/articles.x/13741/4<]§

    • matic
    • 11 years ago

    So Intel will still be faster than AMD compared bug for bug?

      • Scrotos
      • 11 years ago

      Intel has higher IPC but AMD has better IPB throughput?

    • ssidbroadcast
    • 11 years ago

    q[

      • Traz
      • 11 years ago

      and possibly the groin area

        • ludi
        • 11 years ago

        Why stop with the groin? Might as well move down to the Harding Special from there…

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