Much like DDR SDRAM, though, Rambus has devised a scheme to push their memory technology into the world of quad-pumped signaling. This technology, according to Rambus, has been in development since 1997. They also claim they've been able to demonstrate this technology to "key OEM and semiconductor parters." If their claims are to believed, this isn't yet another "five years from now" technology.
According to HardwareCentral and this Rambus PDF, RSL and QRSL are not just limited to memory technology, either. Their overall design could allow for a high-speed, high-bandwidth, and fully signal-compatible front side bussomething our own Ronald Hanaki shared with us yesterday in this news article about Intel's license leeway with Rambus. Most importantly, he reminded us that AMD has a Rambus license, as well.
Certainly interesting technology and interesting thoughts to consider, but there seem to be some caveats to it all. If I understand correctly, QRSL implemented today would be a 200MHz quad-pumped bus. Presumbably, if used in a memory interface, you would have the typical 16-bit interface. When used as a memory interface, current RSL technology works at 400MHz on a double-pumped bus with the standard 16-bit interface.
It would seem logical that a increase in bits per clock cycledespite a unchanged bandwidth and speedwould be benficial. But is that true? Or would it only be beneficial in certain scenarios? There must be more to be had about this technology and its operation. Feed me, Seymour. Feed me.
Thanks to AngryM0nk3y for the interesting read.