AMD to support Intel’s AVX instruction set

Future AMD processors will support the same AVX instruction set as Intel’s next-gen Sandy Bridge CPUs. AMD Senior Architect and Fellow Dave Christie made the announcement on AMD’s Developer Central blog this morning, saying his company has shifted focus away from SSE5 in an ostensible effort to make things easier for software developers.

First, a quick refresher: in August 2007, AMD announced SSE5, an instruction set it said would materialize as part of the Bulldozer architectural refresh two years later. In March 2008, Intel revealed that Sandy Bridge—the next major architectural refresh after Nehalem—would include a new instruction set dubbed Advanced Vector Extensions, or AVX. Intel published the AVX spec (PDF) the following month. Finally, in November 2008, AMD posted a new roadmap showing it had postponed Bulldozer until 2011.

According to Christie, AVX brings “somewhat different” implementations of some of SSE5’s features—particularly “the three- and four-operand capabilities, the Fused Multiply/Add instructions, and some of the permute instructions.” However, Intel’s spec also contains other enhancements: double-width SIMD floating-point operations, non-destructive three-operand support for legacy SSE instructions, and enlarged opcode space for future extensions. Because of the overlap and the extra AVX features, AMD felt compelled to support the Intel extensions.

That doesn’t mean the smaller chipmaker has turned its back on SSE5 altogether, though. Christie says SSE5 “was based on months of discussions with [software vendors] on what sort of capabilities they felt were needed,” so features that weren’t duplicated in the Intel AVX spec will live on in AMD’s new XOP, CVT16, and FMA4 extensions. (The blog post covers those in more detail.)

Christie doesn’t say which AMD processors will support AVX, XOP, and the other new extensions, but it’s probably reasonable to expect them in the first Bulldozer CPUs in 2011. Intel, meanwhile, plans to have AVX-toting Sandy Bridge processors out in 2010. Both Bulldozer and Sandy Bridge will debut on 32nm silicon. (Thanks to The Register for the link.)

Comments closed
    • BoBzeBuilder
    • 11 years ago

    We’re stuck with the Phenom for TWO MORE YEARS?
    AMD <da FaiL.

      • Flying Fox
      • 11 years ago

      Phenom II seems to be shaping up as a pretty good CPU. Phenom I is almost about to be forgotten.

        • My Johnson
        • 11 years ago

        The enlarged L3 cache helps it a lot.

    • tygrus
    • 11 years ago

    Intel not designed here.
    Intel was also working on the next instruction set extention, they saw what AMD was proposing and they knew they had to make something better. So if AMD didn’t make the release we might have been offered less. Intel have now given themselves the lead because they can details the specs as they design the silicon where as AMD will have to finish the design after Intel has released a product. If AMD doesn’t delay, Intel may change the spec to suit it’s implementation and AMD may not be able to complete all features and errata.

      • UberGerbil
      • 11 years ago

      Intel can’t go changing things too late in the game — that’s a good way to piss of software developers (who will mostly be using Intel’s libraries, at least at first, but there’s always an important — and very vocal — group who code right to the metal). As the primary implementor Intel has a lead, yes, but it’s not as much as you might think. Anyway, AMD appears to have much bigger bottlenecks in getting new products out the door.

      As for the design, AVX is significantly different — and markedly better, and more inventive — than AMD’s more conventional and incremental proposal. Regardless of the timing and motivation, the right spec won.

        • Flying Fox
        • 11 years ago

        Adding to UG’s point. The spec was been published last year, so AMD has plenty of time to implement it in their CPUs. It is not like a few instructions can lead AMD to re-architect the whole thing. That is not going to happen and most likely unnecessary.

    • Ushio01
    • 11 years ago

    I guess the article in the below link is well off then. I was so looking forward to AMD catching up as well.

    §[<http://www.brightsideofnews.com/news/2009/4/15/amds-next-gen-bulldozer-is-a-128-bit-crunching-monster.aspx<]§

      • Goty
      • 11 years ago

      This doesn’t change the fact that Bulldozer should be a large improvement. It’s not like AMD is just ditching all of the instructions that would help improve their performance, they’re just deciding to support Intel’s instruction set (which has plenty of overlap as well as some additional types of instructions).

    • leor
    • 11 years ago

    i’m diggin the picture 🙂

    • UberGerbil
    • 11 years ago

    This was inevitable; I’m just surprised AMD caved so soon. I guess they’re not in a position to stand on pride. The AVX spec is technically far superior to SSE5, and the instruction encoding was going to cause problems for AMD over the long term if they didn’t adopt it. A common set of extensions will be more quickly and widely adopted by developers, so everybody wins.

    AVX is the next step in SSE, but it’s a very big step — bigger than anything since SSE2 added floating point and the XMM registers. It finally delivers on a lot of things — particularly FMA and some other 3 and 4 operand instructions like permute — that made SSE inferior to the vector extensions in many other modern ISAs (such as AltiVec). And it makes it possible to do even more operations in parallel. So it’s one more step towards high performance computing for x86 (and one more nail in Itanium’s coffin). It’s not perfect, and it’s not complete, but it is a big improvement.

    (Note that this is entirely separate and different from the new vector instructions that Larrabee is using).

    Just wondering aloud: when the AVX spec came out some folks speculated that Intel’s wholescale plunge into FMA and 3+ operand ops — one of Itanium’s last bailiwicks — was a sop to Apple and its ISVs, a fair number of whom have never stopped complaining about the loss of those instructions along with Altivec when Apple went x86. (The increased performance of Core made the loss fairly painless in real terms, but it’s hard to shut up a programmer who thinks he’s tasted “elegance” and then has to forgo it) To the extent that was true, it may have added weight to AMD adopting the spec sooner rather than later, if they still have hope of getting any Apple business in the future.

    BTW, there was a pretty good (albeit quick and dirty) comparison of SSE5 vs AVX posted by a commenter at realworldtech last year:
    §[<http://realworldtech.com/forums/index.cfm?action=detail&id=91619&threadid=91619&roomid=2<]§

      • Flying Fox
      • 11 years ago

      AMD probably won’t mind if they can get some of the fallout from the further killing of Itanium. Will be interesting to see what Intel can do to keep Itanium as king of the HPC hill, like even more cache or some other crazy ideas?

      I always thought predicated execution is a good thing, has that been proven to have a significant advantage over conventional branch prediction-rollback stuff?

        • UberGerbil
        • 11 years ago

        I honestly haven’t been keeping up on the details of the Itanium world, so I don’t know what the verdict is wrt its particular implementation of predicated execution. It does require bigger caches, which drive up cost, and it’s bad for power efficiency, so hurts TCO that way also.

    • Meadows
    • 11 years ago

    Nice description about AVX, but what does it actually do?

      • stmok
      • 11 years ago

      It’ll improve floating point performance…In an ideal case, up to 2x over current processors.

      Which is good for: multimedia work, 3D modeling, scientific simulation, and financial analysis.

        • UberGerbil
        • 11 years ago

        In the ideal case it’ll be more than 2x at constant clockspeed. You get 2x from having registers twice as wide (so twice as much data at a time, assuming you can keep it fed), but the new instructions allow you to implement algorithms more efficiently, so you use fewer cycles. How much of a difference that makes will vary, but in a fair number of cases it may be more significant than the gain from the increase in register size.

    • Swollen_Goat
    • 11 years ago

    Step into my parlor said the Intel lawyer to the fly…..err… I meant spider. 🙂

    • barleyguy
    • 11 years ago

    Intel and AMD have a full cross license agreement for all of their instruction sets, signed back when AGP was the new thing. So AMD should normally support all new Intel instruction sets, and vice versa.

    So, no big surprise. Good details though.

      • UberGerbil
      • 11 years ago

      They legally could support them, but they don’t have to. And when they had competing specs, there was no guarantee they would (particularly since AMD had their spec out first — whoever gets new instructions implemented in silicon and adopted by developers typically wins, as x64 demonstrates). AMD certainly could have dragged out things and muddied the waters with a competing but ultimately doomed set of extensions as they did with 3DNow! and that would’ve been bad for everybody. Of course AMD would suffer the most, but there’s an element of pride involved, and they could’ve held out a lot longer than this. It’s good that they didn’t, but it is somewhat surprising they conceded this quickly.

        • sparkman
        • 11 years ago

        Does anyone know if the Intel+AMD cross-licensing agreement applies to Larabee New Instructions?

          • UberGerbil
          • 11 years ago

          The information that would enable us to determine that is redacted from the publicly available patent cross-license agreement between AMD and Intel.

          1.12. “Intel Interface” shall mean *****.

          1.13. “Intel Licensed Products” shall mean *****.

          1.14. “Intel Processor” shall mean *****.

          1.15. “Intel Processor Bus” shall mean *****.

          1.16. “Intel Proprietary Product” shall mean *****.

          etc.

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