AMD reveals more details about Llano processor

The Llano "accelerated processing unit" has been on AMD’s roadmaps for over a year, but surprisingly few details have made it out into the news. To coincide with the International Solid-State Circuits Conference in San Francisco, however, AMD has taken the time to provide fresh technical details and pimp the new design. The folks at EE Times jotted down some of the information.

Llano will include four microprocessor cores, 4MB of L2 cache (1MB per CPU core), and a graphics core on a single die manufactured using GlobalFoundries’ 32-nm silicon-on-insulator process. According to EE Times, the CPU cores will each take up 35 million transistors and 10 mm² of die area. Clock speeds will be upward of 3GHz, and supply voltage should fall in the 0.8-1.3 V range.

AMD will base Llano’s cores on the same "Stars" architecture that powers today’s Phenom IIs. Why not Bulldozer, AMD’s next-generation architecture? When we asked the company that question last year, the company replied that it wanted to use a "well understood, existing core" as the basis for its first 32-nm APU. That decision mirrors Intel’s "tick-tock" execution model, which involves transitioning to new process technologies using existing architectures to minimize implementation snags and delays.

Llano will tread new ground not just with its built-in GPU and 32-nm SOI silicon, but also with new power-management features that will allow each core to fit into 2.5-25W thermal envelopes, "depending on the performance demand." EE Times says those features will include core power gating, which allows each core to be shut off completely from the power supply; improved on-die temperature measurements; and a new clock grid design, which EE Times says "reduced the metal capacitance in the grid by more than 80% and reduced the number of final clock buffers by better than half."

AMD’s latest desktop and mobile roadmaps place the arrival of Llano in 2011 as part of the Lynx and Sabine platforms. On the desktop, Lynx will succeed the existing Pisces and Kodiak platforms that combine Athlon II processors with AMD’s 785G chipset. In the notebook market, meanwhile, Lynx will follow in the footsteps of last year’s Tigris platform.

Correction: Judging by the AMD slides posted at Anandtech, Llano will have thermal envelopes of 2.5-25W per core, not for the whole chip as EE Times states.

Comments closed
    • Chrispy_
    • 10 years ago

    A 3GHz Phenom-II with say, a 750MHz 160-SP IGP would blow Intel’s current i3/i5 offerings out of the water. Granted, this is nowhere near release just yet, but it’s a sign of things to come. At any rate, this is rumoured to have 320+ SP’s, not 160.

    Give a casual user a 1.6GHz PC instead of 3.2GHz PC (all else being equal) and they probably won’t even notice the difference.

    Give a casual user 10 fps at low game detail or 20 fps at medium detail and all of a sudden they’ll be amazed at the difference even a really cheap discrete GPU can currently provide.

    Runescape, WoW (and even a few of the simpler browser-based games in fact) are capable of running current intel IGP’s to choppy framerates. Can you honestly expect intel to be competetive with discrete GPU’s in their IGP’s anytime soon?

      • swaaye
      • 10 years ago

      I’m waiting to see if they can solve the memory bandwidth issue with IGPs. Namely that IGPs have very little of it. A bigger integrated GPU won’t get you jack with today’s IGP bandwidth limitations.

    • Mat3
    • 10 years ago

    So why wait until 32nm? Why not 45nm with a dual core??? Who needs a quad core, especially with a laptop? Even with the latest games, half a quad core just sits there doing nothing. They could have had this out way earlier.

      • Anonymous Coward
      • 10 years ago

      The dual core 45nm version would probably be larger than the 32nm quad core one. Perhaps 32nm is the point that AMD thinks the concept makes economic sense.

    • MadManOriginal
    • 10 years ago

    For the record I’m going to coin a word in case this thing sucks by the time it’s released – r[

      • Game_boy
      • 10 years ago

      I always imagined it was pronounced like the Welsh letter “ll”.

        • VILLAIN_xx
        • 10 years ago

        I read it in spanish as “My name is…” 🙂

    • pogsnet
    • 10 years ago
    • ew
    • 10 years ago

    Any info on how many stream processors the integrated GPU will have?

    • sweatshopking
    • 10 years ago

    the fact that it will be a quad core with a gpu, even if it is 100w, is not too shabby. im sure right now that a system with similar capabilities would consume more. this does seem to be a step in the right direction.

      • cygnus1
      • 10 years ago

      agreed, and with a range of a little over 10w to a little over 100w this thing will be pretty killer considering that includes the power for the cpu, gpu and memory controller

        • NeelyCam
        • 10 years ago

        Not true – the 2.5-25W listed in the paper is the core only, and doesn’t include I/Os, GPU etc.

    • jdaven
    • 10 years ago

    I have been reading about this chip on several websites and I am confused about the power rating numbers: 2.5W to 25W. The slides AMD was showing are dies sizes per core without L2 cache factored in. On the same slide is the power rating numbers.

    Now are these numbers per core also? That means 100W for four cores which is worse than the current Athlon II X4 and that’s not including the on die GPU. That will absolutely suck. If it means 25W total, then that means 4 cores with 1 MB L2 cache each (double the Athlon II X4) and an on-die GPU would be the most power efficient CPU ever.

    I’m confused.

      • tay
      • 10 years ago

      There is a little bit of confusion but it is silly to assume magically that a chip excluding L2/L3 will take 25W. Or is it?

        • khands
        • 10 years ago

        Yeah, it’s in a weird spot, especially since 25W/Core wouldn’t count the GPU or cache, which would make it horribly power inefficient.

      • Cyril
      • 10 years ago

      Looks like you’re right. Post edited.

        • jdaven
        • 10 years ago

        Thanks Cyril for the update. The numbers make a little more sense being per core but the top of the range of 25W is not really that great. This is a 32 nm die chip on a mature architecture. A quad core version of this would be 100W at the max rating for the CPU alone. The Athlon II X4 is 95W which comes out to around 25W/core as well at 45 nm (granted half the L2 cache). Not much improvement and definitely not fit for notebooks at the top of the power rating range. However, at 2.5W/core this is a huge improvement. Maybe these chips will cover both notebooks and desktops over a wide range of clock speeds (1GHz+ to 3GHz+).

          • OneArmedScissor
          • 10 years ago

          It’s noted as a range for a reason.

          There are 25w Athlon II-based quad-cores about to be released for laptops.

          There’s absolutely no reason to assume this is some sort of power hungry monster. They’re trying (and apparently failing) to show that it will scale over a large range of uses.

            • khands
            • 10 years ago

            Make everything as simple as possible, but no simpler. I think they crossed that line.

            • jdaven
            • 10 years ago

            Well according to the updated post by Cyril, these are going to be 2.5 to 25W/per core and not overall. So no matter how you slice it we are looking at 25/50/100W for single/dual/quad at the top of the rating range. Now if the 25W/per core chips are clocked over 3 GHz then these will be power efficient indeed but only intended for desktops for the dual/quad variants.

            • khands
            • 10 years ago

            It may depend on if these chips incorporate the self-overclocking feature as well. It may only hit 25W TDP on a core if it’s OCing itself as the only active core.

          • Hattig
          • 10 years ago

          It could be 2.5W at 2GHz, 5W at 3GHz, and then 25W when the on-die overclocking feature kicks a single core up to 5-6GHz.

          Think about a 35W TDP laptop chip.

          SIngle thread: 25W + GPU + northbridge = 35W at, e.g., 5GHz
          Dual thread: 2x12W + GPU + northbridge = 35W at 4GHz
          Quad thread: 4x6W + GPU + northbridge = 35W at 3GHz

          and an ultra-mobile 2GHz quad at 4×2.5W = <20W including GPU and northbridge.

            • jdaven
            • 10 years ago

            That would be cool. Let’s hope its something like that.

            • NeelyCam
            • 10 years ago

            Yeah, that’s probably it, except that I bet the frequencies are quite a bit lower than what you stated here… The paper is about a single core, and mentions that it “operates at frequencies in excess of 3GHz”. If the core ran faster than 4GHz, they probably would’ve said “in excess of 4GHz”…

            No mention of a “turbo” mode in the core paper, but I’m sure the full chip will have power/frequency management.

            • Buub
            • 10 years ago

            Highly doubtful. Those aren’t power ratings for given speeds of processors. They’re power ranges for the processor running under different speed steppings. So, if the processor is under light load it can reduce its clock and run at lower power. If it gets a high load, it kicks up the clock multiplier and runs at higher power.

            It’s cool that they’ll be able to do this independently per core, and even turn off individual cores completely when idle. That’s a pretty major step forward.

            • NeelyCam
            • 10 years ago

            What’s highly doubtful?

            I didn’t see the presentation, but what I gather from the paper and EETimes article, my guess is that the power consumption range is what the core has with typical silicon when supply voltage is scaled, and the maximum clock frequency is similarly affected. Any fast/slow silicon could possibly be binned for higher max clocks or “e”-type low-power CPUs.

            Yeah – full core powergating sounds like a good step towards superlow idle power.

            The paper also mentions that “actual 32nm photo available by conference” – that means this is fresh off-the-boat 32nm silicon, and the numbers in the paper are predictive, based on simulations rather than measurements, so the power and clock frequencies could still go either way before the final products in 2011.

    • gfos
    • 10 years ago

    I think you skipped a year: Sabine will be the successor of danube platform (which is the successor of the tigris platform).

    • Sahrin
    • 10 years ago

    Here’s something impressive – if AMD makes a 1H10 launch for Llano, they’ll be only 6 months (or less) behind Intel in process tech. Now THAT is a big step forward.

      • thecoldanddarkone
      • 10 years ago

      Did you read it, that’s sample product. Release date of the actual product is supposed to be 1h11.

        • Peldor
        • 10 years ago

        Intel publicly demonstrated 32nm Westmere systems on Feb 10, 2009. Sure it’s Feb 9, but that’s close enough to 1 year ago in my book. AMD is doing better for sure, but they’re not doing THAT much better yet. No need to get all tingly over their (well, Global’s) process team catching Intel.

          • OneArmedScissor
          • 10 years ago

          It’s not exactly of dire importance considering that no one is making “true” use of 32nm yet.

          Intel will still “win” there with the 6 core Nehalems, but where it will really matter is with what’s completely new in 2011.

          They could very well end up neck and neck within just a year’s time.

            • cygnus1
            • 10 years ago

            this

            • Game_boy
            • 10 years ago

            And since Magny-Cours fits 12 cores in the same power envelope as Gulftown’s 6, then it doesn’t even matter that the former is 45nm. The final price, performance and power use of the products is what counts.

            Magny-Cours should be close in performance to Gulftown (12 Stars ~2.2GHz cores to 6 Nehalem 3.33GHz cores with HT).

            • NeelyCam
            • 10 years ago

            The performance could be close. Magny Cours costs a ton of money to make, though… I mean, two 294mm^2 45nm SOI chips cost a lot more than one 240mm^2 32nm bulk chip. I wonder how low they can set the price, and still make a decent profit.

            • Anonymous Coward
            • 10 years ago

            In the server space, I think that profit is not the problem. Gaining the sales is the problem.

            • NeelyCam
            • 10 years ago

            Fair point – margins are larger to begin with, so it’s all about performance.

            • OneArmedScissor
            • 10 years ago

            You’re practically comparing small volumes of sand as a basis for which “costs a ton of money to make.”

            Die size is not a financial issue for them. They’ve been relying almost completely on 45nm for a while, and obviously have capacity to spare.

            Intel don’t have capacity to spare at 32nm, after dumping who knows how many billions of dollars into it.

            You’re always talking about profitability, and AMD are just doing what makes the most business sense for them, not the inverse.

            • NeelyCam
            • 10 years ago

            I’m sure Intel could spare some capacity from 32nm Clarkdales for higher-margin Gulftowns..

            But yeah, you’re right – this probably makes financial sense for AMD. I was just pointing out that margin-wise, there is still a big gap between AMD and Intel because of die costs, and I’m wondering if Magny Cours is too little too late.

            Then again, Bulldozer is only some year away, and then AMD will be able to compete in margins as well.

            • NeelyCam
            • 10 years ago

            I’m confused about your “true use” statement… what do you mean? Westmere /[

          • NeelyCam
          • 10 years ago

          Interesting tidbit from ISSCC: two AMD presenters and one Rambus presenter were all complaining about the IBM-based SOI… they were saying it’s uber hard to design analog circuits on, floating body transistors have a memory effect, body-tied transistors are large and noisy, transistors get updated too often so their designs have to cover a massive process skew range…

        • Sahrin
        • 10 years ago

        Did you read any other stories? AMD is targeting a 1H2010 launch for this part – Intel launched Westmere in 1H2010 as well – January, to be specific. If AMD can make a launch in 1H2010, that would mean they launched process nodes within 6 months of each other – a first, so far as I can recall (maybe 130 was that close because of Fab30’s upgrade cycle?).

          • thecoldanddarkone
          • 10 years ago

          Look at the 4th or 5th AMD SLIDE on Anands site. It’s spelled out. Sampling 1h10, Available from oems in 2011.

            • NeelyCam
            • 10 years ago

            ^ This.

    • Spotpuff
    • 10 years ago

    Does this compete with Atom? Or Ion?

      • khands
      • 10 years ago

      Technically I think it’s supposed to compete with the i3/i5

      • stmok
      • 10 years ago

      l[

      • Welch
      • 10 years ago

      It’s meant to compete with Intels “Westmere” CPU which also has an on-chip GPU, although the AMD variant thats talked about in this article employs much more complicated and supposedly sophisticated manufacturing processes. We will see in due time, I believe both parties are targeting the mobile market with these all included integrated setups (that and a way to ensure that they both sell their GPUs)

        • MadManOriginal
        • 10 years ago

        But by the time it’s out it Sandy Bridge will be out too. Intel doesn’t seem to keen on pushing their newest CPU architecture downmarket quickly though unless forced to – maybe Llano will but it will need improvements over Phenom II architecture to do so.

Pin It on Pinterest

Share This