Brought to light: secret Rambus documents

Electronic News has the goods. Some excerpts:
“Finally, we believe that Sync DRAMs infringe on some claims in our filed patents; and that there are additional claims we can file for our patents that cover features of Sync DRAMs. Then we will be in a position to request patent licensing (fees and royalties) from any manufacturer of Sync DRAMs. Our action plan is to determine the exact claims and file the additional claims by the end of Q3/92. Then to advise Sync DRAM manufacturers in Q4/92.”

DRAM makers say they were not informed of Rambus’ plans until after 1997.

“…As far as intellectual property issues go here are a few ideas: 1) DRAM on a packet oriented bus 2) DRAM with low swing signaling 3) DRAM with a two wire initialization system 4) DRAM with programmable access latency 5) DRAM with on-chip address space decoding.

“We may want to walk into the next JEDEC meeting and simply provide a list of patent numbers which have issued and say ‘we are not lawyers, we will pass no judgement of infringement or non-infringement, but here are our issued patent numbers, you decide for yourselves what does and does not infringe.’ On the other hand we may not want to make it easy for all to figure out what we have, especially if nothing looks really strong. If we have a really strong one that has issued that is key to the operation of the SLDRAM, then we may want to play that card, but again with the above suggested disclaimer.”

Rambus patented programmable latency, one of its key SDRAM patents.

Much more can be found here. Rambus has responded that it will continue to protect its IP in this press release. CEO Geoff Tate aims to capture 10% of market share by year end in a webcast dated February 15.
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