Micron integrates ECC controller into next-gen flash memory

Moving the production of NAND flash memory to finer fabrication processes is sure to drive down the price of SSDs. The more memory chips can be squeezed onto a wafer, the cheaper each one becomes. Next-generation solid-state drives are expected to use NAND chips built on 25-nano process technology, and as one might expect from the cutting edge, there are some challenges associated with the shift.

As this article over at AnandTech points out, flash endurance and error rates present bigger problems as the size of each NAND cell shrinks. The move from 50- to 34-nm NAND cut the write-erase cycle endurance from 10,000 cycles to just 5,000, and the 25-nm flash chips currently coming off the line are reportedly lasting only 3,000 cycles. There doesn't seem to be a solution to weakening write-erase endurance, putting the onus on controller designers to devise ways to lower their write amplification factor. I expect we'll see more solutions like the compression-infused black box of technologies inside SandForce's SF-1000 series SSD controllers.

In addition to running out of steam before their 34-nm predecessors, 25-nm flash chips also have higher error rates. Rather than requiring drive makers to combat this at the controller level, Micron has introduced a family of ClearNAND chips that integrate a 24-bit ECC engine. The chips themselves appear as standard flash devices, making the error correction transparent to the controller. Two flavors of ClearNAND will be available: a standard version with 4-way command queuing and transfer rates up to 50 MT/s, and an enhanced derivative that'll queue 16 commands and push up to 200 MT/s. The former will be available in 8-32GB capacities, while the latter starts at 16GB and goes up to 64GB. I expect we'll find enhanced ClearNAND in more than a handful of next-gen SSDs, perhaps including Intel's follow-up to the X25-M G2.

Tip: You can use the A/Z keys to walk threads.
View options

This discussion is now closed.