GlobalFoundries changes plans for 20-nm process

It looks like GlobalFoundries, IBM, and other Common Platform members have done a little soul searching and decided to abandon the gate-first manufacturing approach they’ve been championing for some time. AMD and GlobalFoundries have made it clear that they’re committed to gate-first manufacturing through the 28-nm half-node, but as Real World Technologies’ David Kanter reports, GlobalFoundries’ 20-nm fab process will be a gate-last one.

The specifics are a little above my head, but another article by IMEC explains that the terms gate-first and gate-last refer to “whether the metal electrode is deposited before or after the high temperature activation anneal(s) of the flow.” Kanter points out that both Intel and TSMC have adopted the gate-last approach, while IBM and GlobalFoundries were pursuing gate-first becaused of purported density advantages that “overshadow the defectivity and performance benefits of gate last.”

No more of that. Kanter says some folks are partly blaming the gate-first approach for delays in GlobalFoundries’s 32-nm ramp, and he reckons switching to gate-last will allow for a smoother ramp to 20 nm. Transistor performance could be higher on a gate-last 20-nm process, as well.

Considering how well Intel has been executing lately, AMD really needs all the help it can get from the manufacturing side. Here’s hoping GlobalFoundries will be able to deliver.

Comments closed
    • just brew it!
    • 9 years ago

    It seems to me that they have a history of gambling on non-mainstream design approaches and process technology, hoping that it will give them an overwhelming advantage. Putting the L2 cache on-die for the K6-III (which was unusual for an x86 CPU back in 1999) and switching to SOI (2001) are other examples of this.

    Unfortunately, being the trailblazer has its risks. And this is probably one of the reasons AMD [i<]also[/i<] has a history of missing their launch dates. Sometimes it does work out though -- switching to an on-die memory controller for the Athlon64 was a pretty clear win. (This was also comparatively low risk, given that they had already produced their own northbridges for the K7 platform...)

    • tejas84
    • 9 years ago

    NeelyCam is always right. Sad that the rabid fanboys don’t see that.

    Glad that IBM and friends are going for gate last. This should help AMD for Bulldozer Next Generation.

    • TurtlePerson2
    • 9 years ago

    I don’t really understand how you could start with the gate in the manufacturing process. Ten years ago the metal gates were actually made of polysilicon, which has a much higher melting temperature than aluminum or copper. Nowadays with true metal gates, it seems to me that the gates would melt in later processing steps. Maybe there’s something I’m missing. My VLSI knowledge is a little limited.

      • just brew it!
      • 9 years ago

      I don’t think they [i<]start[/i<] with the gate; rather, the gate is merely created somewhat earlier in the wafer fabrication than it would be in a "gate last" process. So it would probably be better called "gate earlier".

    • TravelMug
    • 9 years ago

    Hehehe, you said “anneal”! 😀

    • Althernai
    • 9 years ago

    It took them long enough. That said, it’s not immediately clear that this will allow for a smoother ramp — it depends on how easy it is to make the transition (gate-last comes with its own subtleties).

      • NeelyCam
      • 9 years ago

      My immediate concern would be what it means to GloFo’s 32nm SOI and 28nm bulk… these are developed too far to make a drastic change to the fundamental part of the process (the transistor). I’m thinking they realized that gate first isn’t gonna cut it, and are making the big changes to the first process they can (20nm). Meanwhile, they are left scrambling to keep the 32nmSOI and 28nmbulk together…

      I wonder if this is the reason for Llano/BD delays..?

    • NeelyCam
    • 9 years ago

    Was NeelyCam right.. again??!!

    Answer: yes.

      • cegras
      • 9 years ago

      Did you make a vague speculation or do you actually have any idea about the materials science involved?

        • Goty
        • 9 years ago

        Probably the former.

        • NeelyCam
        • 9 years ago

        The speculation was based on stuff people smarter than me have published, presented etc. in conferences and technical forums. TSMC and Intel have been gate last proponents for a long time, and I would consider these companies to be on top of the semiconductor manufacturing process game. (OK, TSMC screwed up recently, but they got their act together.)

        That said, I do have a vague understanding of “materials science involved”. Those with a better understanding, please correct me if/when I’m wrong:

        The argument for gate first is that the design rules are simpler, allow for denser layout and – compared to gate-last – require fewer process steps. The argument against gate first is that the later steps of the process screw up the gate, increasing variation, and that having the gate there from the ‘beginning’ complicates the introduction of strain on the transistor channel (strain improves the mobility of the carriers, improving device speed, drive strength etc.), resulting in lower transistor performance.

        The argument for gate last is that as the gate gets replaced later in the process, any ‘damage’ to the gate until then won’t affect the end product. Also, strain can be customized for each transistor type better, resulting in higher performance. The argument against gate last is that it requires more process steps (i.e., more expensive), and that design rules are more complicated, resulting in less dense layouts.

        EDIT: David Canter has a link to a good article on the differences of different processes – you can find it from the comments section on his IBM announcement news page.

    • KarateBob
    • 9 years ago

    In laymans….The 20nm node must be too dense/complex for gates to still function throughout all of the time/different layers of the fabrication process. So they add ’em later on? Sounds like a complex/expensive fix for a very complex and tiny problem.
    Damage? Computer engineers? Help me out here….

      • bdwilcox
      • 9 years ago

      So what you’re saying is that the ‘Gates’ won’t do their ‘Jobs’?

        • DancinJack
        • 9 years ago

        You deserve thumbs up for that.

          • BlackStar
          • 9 years ago

          Indeed.

          • travbrad
          • 9 years ago

          Or 27 apparently. I think that’s the highest I’ve seen on here. Nerd humor ftw 🙂

        • mutarasector
        • 9 years ago

        I coulda swore I heard some guy hitting a snare drum just now….

        • BoBzeBuilder
        • 9 years ago

        I don’t get it.

          • NeelyCam
          • 9 years ago

          Liar. Even your dog gets it.

        • Wirko
        • 9 years ago

        Exactly, that’s the effect of ‘Damage’ hitting the ‘Gates’.

      • indeego
      • 9 years ago

      Hope you aren’t a documentation writer. Your layman’s needs help.

        • Rakhmaninov3
        • 9 years ago

        Actually his help-needing layman’s makes him like most documentation writers!

      • dkanter
      • 9 years ago

      I didn’t explain it quite as thoroughly as I could have. The problem with gate first is that everything in the gate stack must be able to survive high temperatures and come out intact, with good performance. If I remember correctly, you end up heating to 600 degrees or there about. Unfortunately, this means that you cannot use certain metals in the HKMG with gate first. Intel wanted to use at least one metal that had a lower melting temperature in their process.

      So with gate first, you end up having to heat your gate up substantially, and the temperatures seem to increase the probability of failure for the transistors. Higher failure rates = lower yield.

      Gate last also lets you replace the NFET and PFET gates separately, so you can use different metals (with different stress – which is exactly what you want).

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