The Intel project code-named Larrabee was intended to produce a discrete graphics processor to compete with chips from Nvidia and AMD. When that project was canned, Intel decided to keep the work going by re-targeting its efforts toward the HPC and supercomputing markets, building a many-core processor whose mission would be data-parallel computing rather than graphics. The renewed effort eventually gave birth to a revamped, in-development chip known as Knight’s Corner. Today, in a major sign of progress toward a completed project, Intel has officially attached a brand name to Knight’s Corner and future many-integrated-core (MIC) products in the same vein: Xeon Phi.
Intel says it chose "Xeon Phi" because it wanted its data-parallel compute products to be part of the Xeon family. "Phi" was picked because it "evokes many concepts in science & nature including the ‘golden ratio’ in mathematics."
Beyond the announcement of the brand, Intel reiterated some key details about its plans for Knight’s Corner. The chip will be in production "in 2012" on Intel’s 22-nm process with tri-gate transistors. Knights Corner will ship with more than 50 cores and "8GB+ GDDR5 memory" on a PCI Express card. Intel claims the chip will achieve greater than a teraflop of double-precision compute throughput in Linpack. Notably, that’s the same basic performance claim Nvidia made recently for its upcoming GK110 processor. As a proof of concept, Intel has built a Knight’s Corner cluster capable of 118 tflops of throughput.
In addition to its own efforts, Intel has enlisted the help of a number of key industry players in bringing Xeon Phi to market. Among them is Cray, who intends to use Knight’s Corner-based processors in its own supercomputing products.
Perhaps the most distinctive thing Xeon Phi is expected to bring to the table is its x86 compatibility. Intel claims developers will be able to use standard tools and a familiar programming model to harness the power of its MIC processors. This ease of use could allow Intel to gain a foothold among HPC and supercomputing customers who are increasingly turning to alternatives like Nvidia’s CUDA tool set and Tesla processors in order to realize the potential benefits of data-parallel computing. However, we are somewhat dubious about the ease with which applications can be modified to use the full potential of Intel’s MIC chips. Data-parallel computing often seems to require entirely new algorithms, not just modified data structures, in order to achieve optimal throughput. Only time will tell whether Intel’s x86 compatibility will prove to be a noteworthy advantage in this space.