ARM links SoC components with terabit interconnect

ARM has its eyes set on the high-performance computing market. To help with that mission, it's developed a new interconnect to link multiple cores on a single SoC. The CoreLink CCN-504 Cache Coherent Network is capable of offering up to a terabit of bandwidth to as many as 16 processor cores based on the existing Cortex-A15 or upcoming ARMv8 designs. CoreLink isn't just for CPU cores, though; the interconnect supports graphics processors, DSPs, and other "accelerators," too. ARM lays out the possibilities in the block diagram below.

CoreLink allows connected processors to access each others' caches even in heterogeneous implementations that combine CPU and GPU cores. To bolster that core-to-core communication, the interconnect has 16MB of shared L3 cache of its own. ARM has also designed a new DMC-520 memory controller that plugs right into the interconnect. This controller supports not only existing DDR3 memory, but also the next-gen DDR4 standard.

According to ARM, the CoreLink makes extensive use of power gating and other techniques to curb energy usage. ARM isn't straying from its low-power roots. The firm has plans for multiple versions of the CoreLink interconnect, which has already been adopted by Calxeda and LSI. According to the official press release, the first products to use CoreLink should arrive next year.

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