Micron has started shipping samples of its Hybrid Memory Cube. The technology involves stacking multiple DRAM dies connected by vertical conduits. Underneath the stack sits a logic layer that adds a measure of intelligence to the memory array. The whole thing can be soldered next to a processor or deployed in a DIMM-style module.
Right now, Micron is sampling a 2GB chip built with four 4Gb layers. Hybrid Memory Cubes are supposed to deliver up to 15X the performance of existing DDR3 technology, and this implementation offers a staggering 160GB/s of bandwidth. It also consumes just 70% of the power required by an equivalent chip built with planar DRAM technology. So, yeah, pretty cool stuff.
In addition to shipping 2GB samples now, Micron is prepping 4GB samples for March. Volume production of both chips is expected to kick off later in 2014, and Micron expects the HMC tech to make its way into consumer devices in three to five years. Those implementations will apparently use future generations of the technology, which could mean higher densities, finer fabrication processes, or both. Micron's press release doesn't reveal the lithography process used to build the 2GB chips that are sampling now.
The Hybrid Memory Cube's high density, prodigious bandwidth, and low power consumption make it an intriguing option for chip-level caching. Haswell's GT3e integrated graphics already includes 128MB of eDRAM that sits on the same chip package as the CPU. Just imagine what future generations could do with a 160GB/s pipe to 2GB of local memory, let alone something faster with even more gigabytes under its belt.