SATA, PCIe interfaces collide in SandForce SF3700 SSD controller

SandForce's SF-2000 controller has been around since before SandForce was purchased by LSI. It'll be three years old in February, and the time has come for a replacement. The new hotness is the SandForce SF3700, a single chip that brings native support for both SATA and PCIe interfaces under one roof. LSI says it essentially started over with the SF3700, which is designed to be adaptable to not only different product missions, but also a range of future flash technologies.

Although some of the building blocks are familiar, the controller has been completely re-architected. It's now modular, with distinct front-end, core, and back-end components. The front end has dual host interfaces: one 6Gbps Serial ATA and another with four lanes of PCI Express 2.0. SSD makers can configure the controller to use either interface. The M.2 reference design for notebooks even includes a jumper for switching between the two.

Both host interfaces support AHCI, ensuring compatibility with legacy software. The PCIe link also works with NVM Express, an SSD-optimized alternative that promises better performance. There's no mention of SATA Express, though. The latest SATA spec has two lanes of Gen3 PCIe connectivity that should deliver equivalent bandwidth to the SF3700's four-way Gen2 link. We're waiting to hear back from SandForce about how the chip will work with future SATA Express hosts.

The core of the controller is the brains of the operation. It houses DuraWrite, the black box of compression magic that has long been a staple of SandForce controllers. DuraWrite reduces the flash footprint of incoming writes, preserving precious write-erase cycles. LSI says the latest implementation has a "higher data reduction capability." The controller's block selection and garbage collection routines have been improved, as well, and there are now dual 256-bit AES encryption engines instead of just one.

All told, the SF3700 has 14 "cores" dedicated to various functions. The individual processors combine off-the-shelf hardware with custom LSI code, and they're capable of powering down when not in use. Entire portions of the chip are contained within power islands that can turned off separately. These power-saving measures are designed to preserve battery life in mobile applications, of course, but they can be disabled to ensure the lowest possible latencies for enterprise-oriented products.

LSI is particularly proud of the SF3700's low access latencies for prolonged workloads. The chip runs faster than the current generation, according to the firm, but we didn't get specifics on clock frequencies. LSI did, however, confirm that the controller's internal buffers have been expanded. These internal buffers allow SandForce chips to get by without separate DRAM cache memory. They're now large enough for the controller to address 2TB of flash.

At the back end of the controller, the flash interface has been completely redesigned. Interestingly, LSI revealed that the old SF-2000 controller's eight parallel NAND channels are split between only two sub-controllers. The SF3700 has a dedicated sub-controller for each of its eight primary NAND channels. It also has an extra, ninth channel.

The ninth channel comes with its own sub-controller, too, and it can be used to improve performance. However, its primary mission is to allow drive makers to offer so-called binary capacities—256GB instead of 240GB or 1TB instead of 960GB, for example—without sacrificing overprovisioned area or RAID-like data protection.

The controller's RAISE protection scheme is designed to recover data lost due to physical flash failures. There are now two modes of operation. RAISE 1 protects against a single page or block failure and consumes one die's worth of capacity.  RAISE 2 can withstand multiple page and block failures in addition to the failure of an entire flash die, but it'll cost you two dies' worth of storage. If a RAISE 2 config encounters a die failure, the drive can either fall back to RAISE 1 mode or maintain level-two status by cannibalizing its overprovisioned area to store redundancy data.

RAISE is the last line of defense against flash errors. The SF3700's back end also features a suite of error correction technologies that SandForce shared with us in August. The most intriguing of these is the adaptive ECC algorithm, which devotes additional bits to error correction as the flash becomes more error-prone with age. When the NAND is fresh and error-free, less capacity is reserved for ECC, increasing the pool of overprovisioned area available to accelerate performance.

Robust error correction is becoming increasingly important as finer fabrication processes churn out flash with lower write endurance. LSI says the SF3700 will support multiple sub-20-nm NAND generations, and it points to the SF-2000 family as proof of its ability to adapt to new flash tech. Like the SF-2000, the SF3700 is compatible with SLC, MLC, and TLC NAND based on both the ONFI and Toggle DDR standards. It's unclear whether the controller supports hybrid configurations that address portions of the flash with different per-cell bit counts, though. We've asked LSI for clarification.

Although the SF3700 controller is a single chip, it will be available in multiple configurations. Some of those configurations will have various features disabled. The most intriguing variants for enthusiasts will be the SF3729, which will come with SATA and PCIe x2 connectivity, and the SF3739, which will drop SATA in favor of four lanes of PCI Express. The entry-level market will be served by the SF3719, while the SF3759 will provide a "scalable PCIe" interface for serious enterprise applications.

Along with four chip variants, LSI has cooked up the three reference designs pictured above. SSD makers have access to plans for M.2 and 2.5" drives that offer SATA or two-lane PCIe connectivity. They can also get their mitts on a half-height, half-length PCIe implementation with a two- or four-lane PCIe link.

We won't see the first SF3700-based products until the first half of next year. The chip is currently sampling to LSI's partners, though, and the preliminary performance numbers are impressive. LSI claims sequential read and write rates up to 1.8GB/s. It also says the chip can push 150,000 random read IOps and 81,000 random write IOps. Those numbers come from a PCIe implementation with 100% incompressible data, by the way. SATA performance is understandably lower: 550/502MB/s for sequential reads/writes and 94/46k IOps for random I/O.

I'm curious to see whether products based on the SF3700 have quicker application load times than the current crop of SSDs. We asked LSI if there's any room for SSDs to provide perceptible performance improvements for typical desktop tasks, and the firm suggested that the higher read speeds offered by PCIe implementations, coupled with the full-duplex nature of that interface, could yield some nice benefits. LSI seemed more bullish on performance improvements leading to lower power consumption rather than a perceptible increase in storage speed. If the controller services I/O requests faster, it can spend more time in low-power states, which can save battery life in mobile systems. That's something we should be able to test when we get our hands on SF3700-powered SSDs next year.

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