Leak suggests PCIe 3.0 coming to next-gen Intel chipsets

For years, Intel’s core-logic chipsets have been limited to Gen2 PCIe. The older interface persisted even as the firm’s CPUs adopted faster Gen3 lanes. However, the latest leak suggests the next generation of chipsets will finally join the party. VR Zone’s Chinese site has posted a series of official-looking slides indicating that next year’s "100 Series" chipsets will support PCI Express 3.0.

According to the slides, the flagship member of the family will be the Z170, which reportedly has up to 20 lanes of PCIe Gen3 connectivity. That sounds like an awful lot, but I count only six lanes reserved exclusively for PCIe slots and devices. Most of the lanes appear to be shared with the chipset’s USB, SATA, and Ethernet interfaces.

Those other interfaces are apparently getting a boost, as well. The slides show the Z170 with up to three PCIe storage ports, three SATA Express ports, and 10 USB 3.0 ports. Each PCIe storage link can have up to four lanes, while the SATAe connectivity is limited to two. All of those storage links will evidently be covered by Intel’s RST drivers. The standard PCIe lanes should also support storage devices, but software support will probably have to come from the OS or third-party drivers.

Like previous Intel chipset families, the 100 Series includes multiple variants, each one with a different subset of the flagship’s features. It looks like the actual chip has 26 high-speed I/O lanes that can be reconfigured and disabled selectively. Six of those lanes are shown as USB-only, while the remainder can be assigned to PCIe, SATA, or LAN duty. The arrangement looks pretty slick—and perfectly suited to Intel’s M.O. of using a single chip to underpin a range of different products.

Comments closed
    • NeelyCam
    • 8 years ago

    Ivy Bridge had PCIe3.0 on the CPU – this article is talking about the (non-CPU) “chipset” (can it still be called “southbridge”?) that so far has had only PCIe2.0 on it

    • NeelyCam
    • 8 years ago

    Ivy Bridge had PCIe3.0 on the CPU – this article is talking about the (non-CPU) “chipset” (can it still be called “southbridge”?) that so far has had only PCIe2.0 on it

    • trek205
    • 8 years ago

    have I lost my mind? I thought we have had pcie-3 in Intel chipsets for over 2 years now.

    • mganai
    • 8 years ago

    PCIe 3.0 has already been there since Ivy Bridge. They’re just adding 4 lanes.

    • UnfriendlyFire
    • 8 years ago

    Heh. Someone on TR determined that a GT 730 is slower and has poorer overclockability compared to the GT 630 in one of the GPU discussion threads.

    Makes sense if you’re in the marketing department.

    • the
    • 8 years ago

    Haswell-E is going to reportedly use the X99 chipset which is a bit different beast altogether. It’ll finally integrate USB 3.0 into the enthusiast chipset and have upwards of 10 SATA 6.0 Gbit ports. SATAe support is currently an unknown but it news hasn’t leaked yet about it on X99, I’d bet against it.

    The server version of the X79, the C600 series, already supports a higher bandwidth CPU-to-chipset link via an optional 8x PCIe 2.0 side channel on top of the regular DMI bus. In the case of Gigabyte’s X97S-UP5 motherboard, the DMI bus can be configured to run at PCIe 3.0 speeds.

    • arunphilip
    • 8 years ago

    So we continue with DMI, and QPI remains on the -E and server platforms only? Sigh.

    • mczak
    • 8 years ago

    I think direct device <-> device transfers are possible (hence the chipset <-> cpu bottleneck wouldn’t matter) though I suspect in practice they aren’t used a lot.
    But presumably scenarios where you’d really benefit from higher chipset <-> cpu bandwidth are limited, and in that case intel will happily sell you a cpu from the server / enthusiast platform (which have way more pcie connectivity on the cpu directly).

    • Vaughn
    • 8 years ago

    So the question that I have is what will we be seeing on the Haswell E boards coming out in the fall. That is my next upgrade am I better off waiting until sometimes in Q1 2015 so see if a better version of these boards will be released?

    • cmrcmk
    • 8 years ago

    If that’s the case (still 4 lanes) then all these extra lanes hanging off the chipset make more bandwidth available to different connections only when they’re not competing with other connections. That means this chipset is basically a PCIe switch with some extra PHYs onboard.

    • the
    • 8 years ago

    PCIe 3.0 also changes the bit encoding from 8/10 to 128/130. The encoding overhead of 8/10 on PCIe 2.0 makes only 4 GT/s of the 5 GT/s usable. Thus usable bandwidth doubles.

    • crabjokeman
    • 8 years ago

    The next gen will probably be 200 series. If you’re expecting model numbers to make sense, you must be new to TR…

    • hansmuff
    • 8 years ago

    Wikipedia says Skylake has DMI 3.0 operating at 8 GT/s. Current DMI 2.0 is 5GT/s.
    I don’t know how wide the transfers are, but diagrams show Haswell i7 with 20Gb/s bandwidth total, or 2.5GB/s, so 4 bytes/transfer. I assume the transfer width isn’t changing.

    I assume it is the bidirectional maximum transfer rate, so you end up with something like 1.25GB/s to the CPU via DMI 2.0.

    If my assumption is true, Skylake DMI has 8 * 10^9 * 4B per second transfer, so 3.125Gb/s or 1.5625 GB/s each direction. Take that with a grain of salt; I tried finding precise information and this is the best I could come up with…

    Either way it looks like Skylake DMI improves by 60% just going by the GT/s figure.

    The number of ports is a convenience and marketing feature really. It’s not engineered such that all ports could run at maximum throughput all at once. Maybe the server parts have faster DMI, I don’t know. I really wouldn’t worry too much about DMI.

    • mczak
    • 8 years ago

    Not even close (if you’re talking peripherals <-> cpu bandwidth). Currently intel is using DMI 2.0 which is essentially 4-lane pcie 2.0. CPUs using 100 series chipsets though (skylake) should get an upgrade to DMI 3.0, which ought to be essentially pcie 3.0, presumably still 4-lane.

    • Ninjitsu
    • 8 years ago

    Yeah the naming is odd. Should have been 107.

    • MadManOriginal
    • 8 years ago

    Z170 doesn’t make sense to me…shouldn’t it be Z107?

    Also, 3 PCIe and 3 SATAe makes for a hell of a lot of regular SATA ports.

    • willmore
    • 8 years ago

    I didn’t see anything about the link back to the CPU being upgraded. Is there enough BW there to support 20 PCI-E 3.0 links?

    Edited to add: Thanks, everyone, looks like, at best, it’ll have 2x the current BW of 4 PCI-E 2.0 lanes. So, that’s a 5 to 1 oversubscription over the CPU<>chipset DMI link.

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