CPU startup claims to achieve 3x IPC gains with VISC architecture

A Silicon Valley startup known as Soft Machines has just exited its "stealth" phase and is presenting at the Linley Microprocessor Conference today. The firm is introducing a new CPU architecture that it calls VISC.

In its press release, Soft Machines claims that the "VISC architecture achieves 3-4 times more instructions per cycle (IPC), resulting in 2-4 times higher performance per watt on single- and multi-threaded applications" than today's CISC- and RISC-inspired CPU designs. Those claims are attention-grabbing, since Intel's high-end CPUs have been limited to per-clock performance gains on the order of 5-15% for a number of generations.

The press release doesn't go into any great detail about how VISC works, but it does offer some sense of what's involved:

The VISC architecture is based on the concept of "virtual cores" and "virtual hardware threads." This new approach enables dynamic allocation and sharing of resources across cores. Microprocessors based on CISC and RISC architectures make use of "physical cores" and "software threads," an approach that has been technologically and economically hamstrung by transistor utilization, frequency and power-scaling limitations.

If this architecture can bunch together groups of disparate execution units and registers in order to accelerate the execution of a single software thread, it could turn out to be something truly interesting. That seems to be the claim the firm is making. Here's more from  President and CTO Mohammad Abdallah:

"We founded Soft Machines with the mission of reviving microprocessor performance-per-watt scaling. We have done just that with the VISC architecture, marking the start of a new era of CPU designs," said Soft Machines co-founder, president and CTO Mohammad Abdallah. "CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. The VISC architecture solves this problem 'under the hood' by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading." The VISC architecture scales by changing the number of virtual cores and virtual threads. This approach provides a single architecture capable of addressing the needs of applications spanning from the Internet of Things (IoT), to mobile, and to data center markets.

VISC relies on a "light-weight 'virtual software layer'" to do its work. As a result, Soft Machines says, existing software should be compatible with VISC-style CPUs.

Not only is Soft Machines announcing its invention to the world, but it's also demonstrating a proof a concept in action at the Linley conference: a "dual virtual core VISC" SoC prototype meant to showcase IPC improvements.

If it works, VISC could be a boon for a large swath of the CPU industry. Soft Machines describes itself as being in the business of "licensing and co-developing" VISC products for a range of markets. Some familiar names may be at the front of the line for any licensing deals. Soft Machines says it has raised "over $125 million in funding to date" and counts among its investors Samsung Ventures, AMD, and Mubadala (the Abu Dhabi development company that owns GlobalFoundries).

We hope to learn more about the specifics of the VISC architecture soon.

Comments closed
    • Theolendras
    • 5 years ago

    Sound like TSX on steroïds.

    • tipoo
    • 5 years ago

    So IBMs Power8 employs a concept similar to this, if the workload is optimal for it you can either have one “big” thread using all the execution resources, or up to four (edit: Eight) smaller threads with higher total throughput. Am I wrong? The difference, it seems, would be that this would scale up past eight?

      • the
      • 5 years ago

      A little off. POWER8 goes up to 8 threads per core and has the ability to dynamically change the number of concurrently running threads. So as long as there are additional threads to run, a single POWER8 core can scale in performance. In fact, there are enough execution resources in a POWER8 that it seems like a single thread can’t saturate execution resources.

      This VISC architecture essentially takes a single thread and is able to spread parallel parts of the code as multiple threads. One way to look at VISC is ‘reverse hyper threading’ but that over simplifies many of the fine details. There is a bit of code morphing involved to optimize towards the underlaying hardware and to spread out a single threaded workload across multiple cores.

    • the
    • 5 years ago

    A bit more information can be found [url=http://www.eetimes.com/document.asp?doc_id=1324364<]here at the EETimes[/url<] and a [url=http://www.softmachines.com/wp-content/uploads/2014/10/MPR-11303.pdf<]copy of a Micro Processor Report article (PDF)[/url<]. The first big take away I have is that the high level CPU core design looks a lot like AMD's Bulldozer. There is a shared global front end with shared L1 instruction cache, branch predictors and decoders. Then there are two cores with dedicated data cache and back end execution units. The other part of the design uses techniques found in Transmeta's code morphing (also similar to nVidia's Denver compute model) to do binary translation. This is where a single thread is broken down into parallel threads that run concurrently. The MPR article also mentions a 'dual core' test chip that was achieving an IPC of 2.1 vs. 0.79 on a Cortex A15 vs. 1.39 on Haswell. The big kicker is that clock speeds used for this comparison were not disclosed so even it was able to achieve a higher IPC, the other architectures could have easily outrun the prototype chip. (I should add that being a slow prototype isn't that bad at this stage since it is just a proof-of-concept design.) The real deflator of hype should be that their simulation of a four core design running a single thread only doubled performance - Amdahl's Law strikes again. SMT on the cores would further increase efficiency. So the idea of 'they solved multithreading by using multithread' is apt. Ultimately this just feels like a more efficient form of SMT where loop unrolling is spun off into an independent thread that can run on a different core. Power efficiency was not discussed. High IPC and low frequency has proven to be a good means of keeping power consumption in check. However, these low power designs oddly exploit their own low IPC to power gate units to drive energy consumption even lower. Compute efficiency through high execution utilization does not always translate into improved energy efficiency. Again with every architecture, there are bound to be some quirks. I predict that this deisgn's weaknesses will be exposed in highly inter dependent loops. Current multithreaded code that needs lots of coherency I suspect will also show little gains over contemporary CPU designs. The problem is that there is a lot of code that fits these scenarios.

    • sschaem
    • 5 years ago

    Looking at the 3 investors in particular:

    Mubadala
    Global Foundry – 100% owned by Mubadala
    AMD – 25% owned by Mubadala

    Not sure what Global Foundry interest is in this… But there is a strong investor connection.

    I dont have the patience, but I wonder how many of Soft Machine employee use to work for AMD ?
    Couldn’t resist. It seem actually most bio seem to show a Sun microsystem connection.

      • tipoo
      • 5 years ago

      Speaking of AMD investments, did that resonant clock mesh thing ever get integrated into their CPUs?

        • the
        • 5 years ago

        Yes. It was implemented into Piledriver.

        [url<]http://www.eecs.umich.edu/eecs/about/articles/2012/ISSCC_2012_Piledriver_final_submission.pdf[/url<]

          • tipoo
          • 5 years ago

          Ah, nice. I just remembered it being too late for bulldozer.

    • Rza79
    • 5 years ago

    The ExtremeTech article is a bit more thorough:
    [url<]http://www.extremetech.com/extreme/192858-visc-cpu-virtual-core-design-emerges-could-this-be-the-conceptual-breakthrough-weve-been-waiting-for[/url<] The overall negativity seems a bit unjust. The idea makes perfect sense. A lot will depend on their CPU partner since Soft Machines isn't going to design a CPU. For me the idea feels a lot to what happened to GPU's pixel and vertex shaders. Unification of split resources. Instead of having a static split (cores) between your ALUs, FPUs, ... , unify them and assign resources dynamically to a thread, according to it's needs. This is truly the future. No more resources sitting by idle. @sshaem [quote<]And they solved the difficulty of multithreading by offering multithreading ???[/quote<] Actually exactly the opposite. Allow a processor to assign more resources to a single thread than ever before.

      • sschaem
      • 5 years ago

      Back to SMT… Intel HT is doing this already. Multiple HW thread sharing all of a core resource.

      Now if turning a single thread into multiple thread was even possible, then a compiler could do this offline. But a single thread is by design sequential.
      The best that can be done is get some opportunities to re-order instructions, but thats pretty much it.

      Also , the numbers / benchmarks used are deceptive.
      I think if the JPEG example used Intel jpeg decoder haswell would be 6x time faster.
      And if you count SIMD execution as discreet instruction, the IPC of haswell would shoot throught the roof.

      I think the idea of turning 1 thread into 4 thread, running on 4 discreet core is BS,
      but what they could have done is simply have 1 core with SIMD execution units.
      But found a way to leverage scheduling thread per SIMD sub register.

      So the thread feed out of order pipes, and the pipes feed SIMD execution units.
      So anything that can execute out of order, now can execute in parallel.
      And using SMT, you now have a greater chance to fully utilize the SIMD units.

      So as presented, this make no sense. (A thread split into multiple thread is not possible)
      Also the method is no directly applicable to AMD or Intel architecture. So Intel can apply this and get 4x the IPC on haswell.
      But AMD could potentially use this in a future CPU architecture to finally fully leverage SIMD units. (one step closer to unifying GPU and CPU)

    • alrey
    • 5 years ago

    i lost interest when i read “light-weight ‘virtual software layer'”. how can something virtual be fast and efficient?

    • ronch
    • 5 years ago

    Trident XP4 Redux.

    • moose17145
    • 5 years ago

    I am hopeful… but also skeptical.

    Hopefully this lives up to what it promises, and hopefully it actually sees the light of day if it does. But… well… all the things everyone else already mentioned about why they are skeptical of these claims…

    • AMDisDEC
    • 5 years ago

    Virtual CPUs running virtual threads and distinct from CISC and RISC?

    So, it sounds like they have an updated dynamically configured and programmable AMD bit slice engine.

    • Chrispy_
    • 5 years ago

    [quote<]CPU startup claims to achieve 3x IPC gains with VISC architecture[/quote<] We're all sick of startups that make outrageous claims and fail, and these claims are pretty outrageous. If they can prove it in an example thats applicable to real-world software, then perhaps we'll stop assuming this is just a plan to scam some gullible investors.

      • itisworld
      • 5 years ago

      I guess they got working silicon with android ics booted .. thats real software anyhows….

    • UnfriendlyFire
    • 5 years ago

    If those claims are real, this is probably what’s going to happen:

    1. Google buys them.
    2. Apple buys them (for the patents).
    3. Samsung buys them (for the patents).
    4. ARM buys them (which will set off a rabid response from Intel, ex: more aggressive contra revenue, power optimizations and other SoC stuff).
    5. AMD buys them (and chokes on the extra debt)
    6. Intel stops contra revenue for a month to spend some pocket change.
    7. Facebook buys them, because why not.

    Right now it seems like really hyped marketing. Let’s see if they can walk the talk.

    • Voldenuit
    • 5 years ago

    [quote<]addressing the needs of applications spanning from the Internet of Things (IoT), to mobile,[/quote<] Correction: the correct abbreviation for Internet of Things is lol. Like this: bla bla bla Internet of Things (lol).

      • Meadows
      • 5 years ago

      Yes, can we please stop using “the Internet of Things”? It makes me think there’s a whole separate Internet just for all the things. Like a TOR darknet for refrigerators plotting to overthrow mankind.

        • Vhalidictes
        • 5 years ago

        There is a whole separate Internet for IoT. It’s called IPv6.

    • Meadows
    • 5 years ago

    Now I’m not an expert by various stretches of the imagination, but on the face of it, this sounds quite similar to what today’s GPUs are doing, having a bunch of little resources and an intermediate driver layer that dispatches work to them dynamically as it sees fit.

    Except in this case, there are more kinds of little resources on board.

    Assuming I read it correctly, why hasn’t anyone else thought about it before? Is it not possible to make an x86 compatible design this way?

      • Ninjitsu
      • 5 years ago

      Now that you mention it, isn’t Nvidia doing something like this with Denver?

        • itisworld
        • 5 years ago

        There is a big difference wrt to Denver.

      • mesyn191
      • 5 years ago

      That is what OoOE does.

      On top of that modern x86 CPU’s do lots of other stuff like prefetch + use caching and pipeline instruction decoding streams/caches and SMT/CMT.

      What modern GPU’s are doing is very different than VISC. Modern GPUs are doing what amounts to a very wide pipeline + tons of cores with lots of SMT to make up for cache and prefetch deficiencies. That only works because GPU work loads have tons of TLP and ILP. CPU work loads tend to be poor in both + branch heavy which necessitates huge amounts of on die caches and specialty hardware to get better performance. Particularly if you want to use that CPU in a server.

      Also there is nothing stopping you from doing a x86 VISC CPU per se since x86 is just the ISA. Much like how ARM and MIPS were originally RISC ISA’s but now aren’t much different overall than x86 chips in terms of features and have also become similarly large in order to get more performance.

    • LordVTP
    • 5 years ago

    I would really, really like this to somehow be a virtual FPGA with dynamically definable arch and ops. Given a no name company with no physical tech? … I want to believe =\

      • chuckula
      • 5 years ago

      This does have FPGA synthesized written all over it… at least for any parts they want to use for demos. I could see something a little more concrete come out in the long run if this actually works.

        • the
        • 5 years ago

        An FPGA prototype would be appropriate to see if their concepts are worth investing into. Though they do need to be forth coming about this to any investor.

    • sweatshopking
    • 5 years ago

    MAN, I LOVE HEARING FROM YOU CPU EXPERTS. YOU SHOULD HAVE TOLD SAMSUNG, AMD, AND MUBADALA THAT YOU KNOW BETTER AND SAVED THEM THEIR MONEY. IT MUST BE NICE TO KNOW EVERYTHING. HOW COME YOU’RE NOT ALL MILLIONAIRES?

      • albundy
      • 5 years ago

      ROFL! it could be worse…you could have believed them.

        • willmore
        • 5 years ago

        Yeah, about the only thing to make this press release would be to put it in all caps.

      • MadManOriginal
      • 5 years ago

      Depending upon how much of the company they still own, and how they are compensated, they may very well be millionaires already.

        • chuckula
        • 5 years ago

        There’s only one way I know of to become a millionaire that works every single time: Start out a Billionaire.

          • Meadows
          • 5 years ago

          [url<]http://youtu.be/UxVivkXUfdU[/url<]

    • windwalker
    • 5 years ago

    Pontificating over a press release is pointless.
    I want to see the demo first because I only care what it is only after I see what it does.

      • willmore
      • 5 years ago

      I absolutely hate +1’ing this guy, but he’s right this time.

    • YukaKun
    • 5 years ago

    So they’ll be using a hardware scheduler with a low-fat software layer for the OS’es Kernel? I’m trying to take all the PR-BS in those statements and try to think about the CPU itself.

    Also, I wonder what they define as a “thread” and “core”.

    Cheers!

      • Pwnstar
      • 5 years ago

      But…but…they’re VIRTUAL!

    • BobbinThreadbare
    • 5 years ago

    Didn’t AMD say they were going to do something like this a few years ago? Have the CPU/compiler split single threaded taskes up among multiple cores to do it faster?

    If the maker of the 2nd fastest CPUs in the world wasn’t able to figure this out, I really doubt these guys did.

    If they did though, well congrats.

      • chuckula
      • 5 years ago

      [quote<]Didn't AMD say they were going to do something like this a few years ago? Have the CPU/compiler split single threaded taskes up among multiple cores to do it faster?[/quote<] It would be the CPU doing it and it's the semi-mythical "reverse hyperthreading" that you'll find with some googling.

    • tipoo
    • 5 years ago

    Not to be a cynic, but these claims never seem to see the light of the market. Remember clockless chips?

      • chuckula
      • 5 years ago

      Clockless chips were ahead of their time.

        • Neutronbeam
        • 5 years ago

        And always will be ;-).

        And I still prefer chocolate chips.

        • maxxcool
        • 5 years ago

        Bad-dum-bum!

      • hansmuff
      • 5 years ago

      Or Transmeta…

      • willmore
      • 5 years ago

      You’re making fun of Amulet?

      • UnfriendlyFire
      • 5 years ago

      Lots of automated design tools won’t allow clockless designs or require workarounds.

      • auxy
      • 5 years ago

      Remember Glaze3D? BitBoys Oy in general?

      I was a BitBoys fangirl from day one, but nothing ever happened. Bleh.

      This seems like more nonsensical spew full of buzzwords trying to capitalize on the virtualization hype that’s overtaken the market in the last few years.

        • Rza79
        • 5 years ago

        The existence of Adreno is thanks to BitBoys.
        So something eventually happened.

          • Scrotos
          • 5 years ago

          BitBoys! If the Future Crew blokes can’t make a great 3D card, who can?!?

          …oh, plenty of people could.

      • the
      • 5 years ago

      The idea of synchronous logic was something explored in depth for a full CPU by Sun a decade ago. Conceptually it was possible but they never able to get their research chips validated and thus move out of the research/prototype stage. Sun did manage to use some asynchronous logic in the UltraSPARC IIIi’s memory controller.

      OTOH, there have been a few simple microcontrollers that have been released to market using asynchronous logic.

      It’d be interesting to revisit this idea with modern development tools but I suspect the same issue will resurface: some one can design it but they won’t be able to fully validate it for commercial release. Actually Intel did purchase Fulcrum Microsystems three years ago who was a major researcher and patent holder in this area.

    • guardianl
    • 5 years ago

    Extraordinary claims require extraordinary evidence.

    From the little info Soft Machine provided, it sounds like their virtual software layer is similar to Nvidia’s real-time emulation layer for denver (which does some dynamic re-ordering etc.) It’s basically the real-time equivalent of Itanium’s “let the compiler optimize the code” for the most part.

    $20 says that Intel’s CPU cores have faster absolute single-thread performance than anything this VISC “technology” produces (if anything, ever) for the next 10 years.

    • NeelyCam
    • 5 years ago

    IT’S A MIRACLE!!

    They should call themselves “Hard Machines”. That name would be cool
    heh-he-he-heh-he… hard…. heh-he-he-he… cool… he-heh-heh-he..

    • wof
    • 5 years ago

    This seems to be cool, check out the presentation on their homepage.

    It’s like Transmeta on steroids with single thread to multicore conversion of software on the fly or something and they do have working silicon.

    • sschaem
    • 5 years ago

    This seem be to nothing more then a form of dynamic SMT, and thats not really a good idea.

    And they solved the difficulty of multithreading by offering multithreading ???

    “multi-core implementations that require unrealistically complex multi-threading of sequential applications”

    “the VISC architecture solves this problem ‘under the hood’ by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading.”

    – Intel HT is actually VERY efficient. They are very close to full utilization of the HW core.
    So getting 3 to 4 time IPC more out of a core is impossible.

    – Kernel thread switch is minimal (need to find recent numbers) to insignificant.

    – The #1 killer is cache sharing. The more thread you run on a core, the more cache is shared across different thread / process. This is a performance KILLER.

    For Intel, if they had a magic wand, they might be able to squeeze maybe 10% more in IPC with the same architecture. (10% from resource stalling related to instruction execution)

    So the 4x higher IPC is BS.

    Second the more concurrent thread the smaller the cache become for each thread.
    Instruction cache, L1,L2, L3 data cache pressure can cause HUGE speed drop.

    Based on the data so far, it seem like a scam to me…

      • chuckula
      • 5 years ago

      You could have insanely high IPC… by massively sacrificing the “C” and increasing the “IP” with big gobs of hardware execution units that are doing all kinds of over the top speculative instruction on sequential code.

      However, they are promising big performance per watt numbers, and throwing huge sets of hardware at inefficient execution (since you throw away all paths except the correct one) isn’t that conducive to power efficiency….

      • tay
      • 5 years ago

      While I +1’d you, you are missing the forest from the trees. This is not for fine grained instruction level parallelism, but (largely independent) thread parallelism.

        • sschaem
        • 5 years ago

        Remember the claim is a 3x to 4x gain in IPC, by using a method to feed more concurrent thread to a core.

        And also to paraphrased “multithreading is hard, and our solution is more multithreading”

        You also have a catch 22 with having more concurrent thread per core.

        And you can see it even when you have 2 thread per core.

        HT is a huge benefit for under utilized execution units (from stall or simply lack of instruction level parallelism), but the drawback is that all shared resource can be cut in half.
        So you can gain on one side, loose on the other.

        I personally dont see anything will come out of the IPC claim.. unless its maybe related to SIMD ? where they found a way to leverage SIMD execution units in a total different way.

      • fredsnotdead
      • 5 years ago

      If I understand correctly, multi-thread capable CPUs have per-thread registers to make switching more efficient. Why don’t they also have per-thread L1 caches? Or has this been done?

        • chuckula
        • 5 years ago

        Per-thread registers make sense since you have two or more independent program counters with different stack frames and immediate variables that aren’t shared between threads. However, at the cache level that makes much less sense since most of the cached data will be shared amongst threads and you use things like semaphores & mutexes to prevent different threads from clobbering shared data.

        You may be thinking of *processes* instead of *threads*. For processes, the amount of data for two different processes would hamper the effectiveness of the cache in many situations (e.g. you’d turn a 1MB cache into 2 512KB caches for 2 processes, or 4 256KB caches for four processses, etc.)

          • Pwnstar
          • 5 years ago

          What if you use a large cache? 4MB would give 4 processes 1MB each.

            • chuckula
            • 5 years ago

            Sure, but you have to pay the piper one way or the other. Very large caches can work, but they also consume a huge chunk of transistors and high-speed caches use power too. There’s always a tradeoff to be made somewhere.

            • TA152H
            • 5 years ago

            Yes, but the price would be much less than normal.

            One big cost you left out is the speed of the cache. Large caches are necessarily slower, everything else being the same. Multiple smaller caches, based on context, wouldn’t have that issue.

            Also, one could turn off, or really greatly reduce power to, caches not in the current process context.

            The die size is surely a big consequence of this, and pretty unavoidable. You’d also increase the complexity of the processor by adding all this logic, adding more size.

            I’m sure someone at AMD, IBM, and Intel have looked at this, and deemed it unfeasible, in any case. At least at this point in time. So, obviously the price is more than the goods, in this case.

      • Namarrgon
      • 5 years ago

      I thought the same as you (sounds a lot like fancy SMT) – but then I realised that investors like AMD have access to far more data about the process than merely a press release, AND they have people who know a thing or two about CPU design. Clearly they don’t think it’s a scam, so if it is one I imagine it’s a lot less obvious than all that.

      I don’t have anything like sufficient data to make an informed judgement, so I think I’m just going to wait for more info before rashly declaring shenanigans..

      • itisworld
      • 5 years ago

      I

    • blastdoor
    • 5 years ago

    So is the idea here basically infinitely flexible hyperthreading?

    That is, you basically have a massively wide core. If you somehow manage to have a single thread that can take full advantage of it, then great – -you’ve got huge ILP for that thread. But if you can’t get a single thread to fully utilize it (which is almost always going to be the case for anything other than embarrassingly parallel tasks), you keep adding hyperthreads until you use all available resources. Is that the idea?

    If so, I’d say…. not necessarily a bad idea. It could be useful in some contexts. But as with everyone who is looking for money, I suspect they are vastly exaggerating the potential benefit.

      • sschaem
      • 5 years ago

      “I suspect they are vastly exaggerating the potential benefit”

      And it might be exaggerated both ways. Its very possible that the design choice is more a problem then a solution.

      Also if your outline is their design choice.
      You dont need dynamic SMT, because the core design in itself is static.
      The core would be optimal utilized with a matching number of virtual core.

      As presented this makes little sense.

      The only benefit might be reducing kernel switch. But this happen maybe only 100 time per second and uses ~200 cycles?
      So even if they CPU exposed 100 of HW thread to the OS, where the OS never had to do switches, you save 20,000 cycle per second. OF CPU that have 2 billion cycle a second…

      Also the more thread on a core, the more pressure on the cache.
      Cache sharing can be dramatic for performance… So those CPU would need to have large L1 instruction and data cache + huge L2/L3 cache.

    • geekl33tgamer
    • 5 years ago

    CPU start-up may have already overtaken AMD’s 20+ years of IPC performance? Perhaps they should share notes…

      • sschaem
      • 5 years ago

      Seem like they have, and are one of the group of people that gave them $125 million…

      I dont think AMD, Samsung etc.. are stupid. So they might be something of value lurking in all this.
      For example, its possible that some server workload do benefit from exposing HW more thread in one form or another. Even if this give a ~3% gain, its would be worth integrating into a design.

    • chuckula
    • 5 years ago

    [quote<]VISC relies on a "light-weight 'virtual software layer'" to do its work. [/quote<] Oh Rlly?? In that case, run it on my core I7 in emulation mode and show me "only" a... 20 - 30% IPC gain as a proof of concept for your "virtual coars". Edit: [quote<] “CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. The VISC architecture solves this problem ‘under the hood’ by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading.”[/quote<] OMG... THEY ACTUALLY DID THE REVERSE HYPERTHREADING!! Either that or: we showed how parallel hardware can do embarrassingly parallel problems really really efficiently. Now just rewrite all software to be embarrassingly parallel.

    • just brew it!
    • 5 years ago

    Sounds like it may be a variation on Transmeta’s ideas… if so, we’ve been there, done that.

    Is the “2-4 times higher performance per watt” just theoretical, or is it real? Boosting IPC alone isn’t miraculous; doing so while *also* reducing power consumption is much harder!

      • ludi
      • 5 years ago

      Oh good, so I wasn’t the only person who saw the letters “TMTA” materialize over the headline.

      If Intel hadn’t just spent the past few years driving x86 down to mobile device power levels, thus guaranteeing that the display is the controlling factor in battery life, these guys might have a shot at some marketspace. But that ship has sailed.

        • curtisb
        • 5 years ago

        [quote<]Oh good, so I wasn't the only person who saw the letters "TMTA" materialize over the headline.[/quote<] Nope...was definitely my first thought, as well.

      • the
      • 5 years ago

      nVidia’s Project Denver is also following in Transmeta’s foot steps. So far nVidia seems to have exceedingly good integer performance but is crushed by the likes of Apple’s A7/A8 in floating point.

      Power consumption of Denver have yet to be published but should be competitive in performance per watt on integer work loads just based up on its performance lead alone.

        • LordVTP
        • 5 years ago

        That’s not really so clear cut (if your referring to the geekbench numbers), The android version of geekbench used is not armv8 nor used any of the newer SIMD ops. Given the process lead (20nm vs 28nm for Denver) and the extra core and transistor budget on A8x? I’m calling that a victory for Denver.

    • JdL
    • 5 years ago

    “Oh, look! We have optimized software for multiple cores / threads and it’s super-fast!!!!”

    Ok, now let’s see them run a real OS / software on it.

    • puppetworx
    • 5 years ago

    I don’t know a lot about CPU architectures but I do know AMD could really use some IPC improvements. That said, if this is really workable Intel has the cash to just outright buy the company.

      • Vaughn
      • 5 years ago

      Yup if this becomes a threat I can easily seeing intel buying them out and shutting it down. Just how the world works these days.

        • tipoo
        • 5 years ago

        Amd and Glofo (and mubadala who owns a large part of the former and all of the later) are already heavy investors, I wonder if they bought enough stake together to shut down an Intel buyout.

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