TSMC’s 10-nm FinFET process toddles towards validation

TSMC has made an important step on the road to validating its 10-nm FinFET design process with the awesomely-named "Product-like Validation Vehicle," according to a report by Nikkei (in Japanese behind a paywall) that was picked up by Kitguru. The foundry showed a quad-core Cortex A57 proof of concept at the 52nd Design Automation Conference in San Francisco last month. Details are still a little light; the firm didn't discuss real or expected clock frequencies.

Image: Nikkei

Willy Chen, TSMC's deputy director for the Design & Technology Platform division, discussed the progression from the firm's 16-nm process to its "16-nm+" process which improved performance due to a change in the shape of the fins, and then to 10nm. In total, transistor density on the 10-nm node will be up 110% from the original 16-nm design.

The Taiwanese chip maker previously made a joint announcement with ARM stating their intent to produce chips on 16-nm and 10-nm processes. Suk Lee, Senior Director of TSMC's Design Infrastructure Marketing division, has also recently talked more concretely about 10-nm processors reaching validation by the end of the year, with volume shipments in 2017. This announcement may indicate the firm is still on target for that goal.

Ben Funk

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Comments closed
    • ronch
    • 4 years ago

    So just how ’10nm’ is TSMC’s ’10nm’?

    • willmore
    • 4 years ago

    Looking at that die shot, I see what look like three more processor quads, probably A53 quads. They are from the center down to the 6 o’clock position.

    The whole upper right quadrant looks like SRAM or similar (cache+tag).

    A lot of the rest of the blocks look like synthasized logic–graphics cores, probably.

    • NoOne ButMe
    • 4 years ago

    a likely sub 50mm^2 SoC for validation! why not validate with SRAM 1MB instead!

      • Hattig
      • 4 years ago

      Clearly they’ve already done the old SRAM validation already. This means that TSMC are beyond simple 10nm structures, they’re now validating quite advanced designs (albeit on small dies, but a 50mm^2 10nm die can hold as much logic as a 200mm^2 28nm die). This is actually a positive thing for them achieving 2017 10nm designs.

      And that may put them on-par with Intel for 10nm (yeah, yeah, 10nm != 10nm), at least in marketing terms.

        • Ushio01
        • 4 years ago

        Then why not publicly announce SRAM validation?

        You can easily find SRAM validation from 130nm to 14nm from most firms but now with 10nm nothing and 16-14nm SRAM validation happened back in 2009.

    • auxy
    • 4 years ago

    I can translate Japanese content if you need. Just message me! (‘ω’)

      • ronch
      • 4 years ago

      それはいいです。ありがとう。

    • UnfriendlyFire
    • 4 years ago

    I’m sure Apple and other smartphone companies will monopolize the supply of 10-nm chips, and I wouldn’t be surprised if the 10-nm process is specifically for smartphones and tablets.

      • blastdoor
      • 4 years ago

      That would certainly make sense — that’s where the money is. Apple in particular has shown a preference for low clock/voltage and big transistor counts. I suspect 10 nm at TSMC and Samsung are strongly influenced by that (or perhaps Apple’s choices are strongly influenced by what TSMC and Samsung say they can do).

        • UnfriendlyFire
        • 4 years ago

        “(or perhaps Apple’s choices are strongly influenced by what TSMC and Samsung say they can do).”

        You’re talking to a company that sitting on a stupid amount of cash and could buy a couple tech companies with little impact (as long as they can keep up the revenue from the iPhones and iPads).

          • nanoflower
          • 4 years ago

          Apple can have all the money in the world and still not be able to make the process tech for building chips move much faster. We are just at the limit of what we know how to do so it’s going to take time to get 10NM and anything smaller working. Plus Apple isn’t in the business of throwing their money away and buying up a company like Global Foundries or TSMC would be just that. Better to let them spend their money and pick the best solution available at the time.

            • UnfriendlyFire
            • 4 years ago

            No, but they can certainly pay GF or TSMC to optimize the 10-nm process for THEIR usage.

    • blastdoor
    • 4 years ago

    I’m guessing either TSMC or Samsung really will manage volume 10 nm shipments in 2017 (using their definition of “10 nm”). The economics would seem to support them spending the money necessary to make this happen.

    • Ushio01
    • 4 years ago

    So have TSMC shown an actual working 10nm chip? before Intel? or is this just another slideshow?

      • Ninjitsu
      • 4 years ago

      Slideshow. It’s a “validation”, and from what I can tell not even a proper tape out – may be wrong here, it’s kind of confusing.

      Intel on the other hand usually never talk “validation” and “tape-out” – just production, which is why we here about them having trouble.

      If TSMC is having trouble they’ll just say “hey but validation” instead. They don’t have a fixed/expected “cycle” like Intel have, so they usually escape the negative sentiment even if they’re late.

        • blastdoor
        • 4 years ago

        Intel and TSMC have pretty different customers, and so different communication needs.

    • bittermann
    • 4 years ago

    They can’t even get away from 28nm for their high performance nodes. Once that thing hits actual wafers it will be years before all the bugs are worked out. That’s not even bringing up leakage.

      • nanoflower
      • 4 years ago

      Don’t forget all of the issues they’ve had with their 20NM process. Clearly it’s still not quite right as AMD is moving everything to off that process.

        • NeelyCam
        • 4 years ago

        20nm was doomed because planar transistors (without SOI) will just leak like sieves. FinFETs address the leakage problem and suddenly transistors became usable again.

          • blastdoor
          • 4 years ago

          20nm seemed to work fine for Apple 🙂

            • exilon
            • 4 years ago

            When your company pulls 200B in revenue and makes 40B in profit/year, it’s probably easier to stomach the wafer costs and cherry-pick the best dies. For everyone else, not so much.

            • blastdoor
            • 4 years ago

            I seriously doubt that is what’s going on. Apple isn’t going to just swallow the costs of low yields.

            What seems much more likely to me is that Apple’s SOC designs are better suited to TSMC’s 20nm process than other products (like GPUs). This is probably by design, both on Apple’s end and TSMC’s end. In other words, the advantage of all that money is that you get special attention from the foundry to make sure your design works well on their process.

          • BobbinThreadbare
          • 4 years ago

          I thought AMD had developed SOI with IBM.

    • southrncomfortjm
    • 4 years ago

    I’d rather the be working on the smaller fab processes for graphics cards.

      • Anovoca
      • 4 years ago

      who says the aren’t

      • Hattig
      • 4 years ago

      Problem is yield for large die sizes. Even Intel’s 14nm products aren’t very large – under 200mm^2, whereas GPUs tend to scale above that.

      So, expect 14nm (and 10nm) GPUs to be multi-die on interposers, with each die being small, and being part of the GPU (e.g., 2048 shader dies, non-shader logic die, hbm).

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