Intel, Micron introduce revolutionary 3D XPoint memory

At a special presentation today, Intel and Micron jointly announced the introduction of a new type of memory technology called 3D XPoint. Intel VP Rob Crooke and Micron president Rob Adams called this memory the first major new memory technology since the introduction of NAND in 1989.

3D XPoint (pronounced "3D cross-point") is described as a high-performance, very dense, non-volatile memory, and it's meant to help computers get more data closer to the processor. Crooke says it's a thousand times faster than today's flash memory and a thousand times more durable. Compared to DRAM, 3D XPoint is ten times as dense, and it's non-volatile. The initial 3D XPoint memory chips pack 128Gb on each chip, and that number is expected to increase as more layers are stacked on each chip.

The structure of 3D XPoint is a stack of individually accessible cells, between bit lines and word lines, combined with a switching system to manage storage and retrieval. Unlike current memory technologies, 3D XPoint doesn't store information by trapping electrons. Instead, it uses a property change of the memory cell materials itself. Furthermore, this property change uses all of the memory cell material. These innovations allow the memory cells to be shorter, packed tighter, and ultimately stacked higher, increasing density. Intel also says the cross-point architecture allows smaller amounts of data to be written or read in each transaction than is common with NAND. This capability could allow for faster, more efficient I/O.

Intel and Micron anticipate that the new tech will enable advancements in high-performance computing and big-data-crunching applications, where large amounts of high-speed storage close to the CPU ought to be very useful. We suspect that 3D XPoint's non-volatility and DRAM-like speed could allow it to replace DRAM in mobile devices, where the power savings offered by non-volatile memory could make for longer battery life.

Both firms are developing products based on 3D XPoint, and the memory will begin sampling "with select customers" later this year.

Comments closed
    • danny e.
    • 4 years ago

    Technically it sounds good but dang it all why can’t they let steve jobs name the thing?
    Doesn’t anyone have a decent marketing dept?

    • Mr Bill
    • 4 years ago

    Ah, this is the competition to Samsungs 3D Vertical Nand.

      • DavidC1
      • 4 years ago

      You got that wrong. Competition to 3D NAND is guess what, 3D NAND. This is completely different. Intel has 3D NAND coming later too.

      This claims latency that is 1/1000 of NAND devices. Even much higher than HDD to SSDs. This has the potential to replace SSD/HDD, AND RAM.

      Think about how much computers work around memory and storage:
      -Computers takes time to boot because storage is too slow and what booting does is it takes the operating system and loads it into memory. Loading is what takes time. If this works out, no more booting
      -You are doing something, but power goes out. You lose everything. Not with this.
      -If you are working with large data applications, and you go over memory, suddenly your system slows to a crawl. Because its using storage as “virtual memory”. It doesn’t need to do that anymore.
      -Nothing related to “loading into memory” slowdowns. Probably there are games and applications that have significant loading and “transition” times because of this. We won’t have that either.

        • Mr Bill
        • 4 years ago

        Thank you for the clarification. I was confusing this with the Intel 3D Nand article that was posted a while back.
        [url<]https://techreport.com/news/27397/intel-3d-nand-has-32-layers-and-256gb-per-die[/url<]

    • willmore
    • 4 years ago

    I didn’t see any mention of read endurance. Phase change memories tend to have a destructive read–like DRAM. Once read, the data is lost and needs to be rewritten.

    We’re used to reads being free (or nearly so) with FLASH and EEPROM, but that’s not an inherent property of non-volatle memory.

    1000x the endurance of FLASH sounds great, but if you have to pay for reads as well as writes, that doesn’t sound quite as good–it’s still good, but not 1000x as good.

    There was an application in the 90’s that I was working on. We used a serial EEPROM to store some data. An FRAM vendor came in and was pitching their product and showing how much better it was than EEPROM. The EEPROM had a write endurance of 100K to 1000K cycles. The FRAM had a cycle life of 1 billion. So, FRAM was a clear winner? Nope. We did a lot of reads of that memory and a back of the envelope calculation showed that the FRAM wouldn’t have the endurance of the EEPROM due to our read:write ratio.

      • Nevermind
      • 4 years ago

      Well, good thing we invented the memristor!

      (Ducks, angry nerd punches obese woman standing behind me)

    • UnfriendlyFire
    • 4 years ago

    SSD on CPU anyone?

    EDIT: Actually, that’ll be a sorta bad idea, because some game or software developer is going to figure out how to create a program that eats up a ridiculous amount of storage space and thus force users to get an external storage.

    You know those 60+ GB games? Tough luck fitting those on a 120 GB SSD.

    • smilingcrow
    • 4 years ago

    Intel and Micron specifically stated that they don’t intend licensing this to others so what are the implications for AMD?
    I can see why Intel would lockout AMD but is that in Micron’s best interests too?
    Maybe that’s part of the deal they’ve struck at least for a period!
    For certain types of Servers/Workstations not having access to this or something similar would keep you out of the game.
    Maybe AMD will hook up with HP?

      • ET3D
      • 4 years ago

      Far as I understand about licensing, that meant that only Intel and Micron will produce these chips, not that only Intel and Micron will produce devices using them. So likely any manufacturer will be able to add such storage, they’d just have to buy the chips from Intel or Micron.

        • smilingcrow
        • 4 years ago

        That makes sense. There are new instructions for persistent memory which I suppose AMD will be able to license under their existing terms.

    • just brew it!
    • 4 years ago

    Sounds sort of like a combination of phase-change memory and Samsung-style 3D flash. It will be interesting to see if this pans out.

    • MetricT
    • 4 years ago

    Intel’s CPU’s haven’t gotten much faster since Ivy Bridge, up to and including Skylake by leaked benchmarks. It’s reasonable to assume Kaby Lake and Cannonlake are the same.

    So, from a customer’s perspective, why upgrade? This is actually brilliant on Intel’s part, because a) it adds a feature that legitimately helps the user and b) because there are a finite number of writes, it will eventually fail and consumers will have to buy a new CPU.

      • BobbinThreadbare
      • 4 years ago

      I don’t think this is going to work it’s way onto CPU packages.

    • DPete27
    • 4 years ago

    Yup, saw this coming a mile away. Combine the speed of DRAM into non-volatile storage and use the new medium for both functions. Just a few more years and we won’t have DRAM [b<]AND[/b<] SSD's. They'll be one in the same. The ability for integration on-chip/package is nice and we'll see something of this nature on laptops in the near future (many laptops these days are being shipped with soldered-on RAM already), but I can't quite predict how the caveat of requiring expand-ability is going to be handled for desktops/servers moving forward. I think you still need to retain some sort of expansion option. Non-volatile storage add-ons are easy, it'd behave similar to a SSD+hdd dual drive setup that we use today. But what if you need more system "memory" than what's on-board?

    • Firestarter
    • 4 years ago

    So how expensive are these chips going to be? Will this make any other non-volatile medium obsolete?

    • Ninjitsu
    • 4 years ago

    Wasn’t there something a while ago about future Xeon memory controllers supporting NAND as well? Is this why?

    • lycium
    • 4 years ago

    Any kind of non-volatile memory will fundamentally change ALL the software we run, in more ways than I can casually imagine right now (as a programmer).

    Loading will become a thing of the past – everything is always in memory.

      • chuckula
      • 4 years ago

      HP is betting a bunch on memristors to do just that.

        • lycium
        • 4 years ago

        Yup, since a long, long time… Here’s hoping Intel and Micro actually deliver something! So very tired of future tech staying in the future. (Actually, there’s one notable exception by now: “Parallelism is the wave of the future… and always will be.” vs GPUs and other multicore ASICs.)

          • NoOne ButMe
          • 4 years ago

          Intel’s track record on delivering things is pretty good. Dunno about Crucial. Both are better than HP. I think memristers were supposed to be coming in 2013, than 2014, than 2015, think currently they say 2016.

        • BlackDove
        • 4 years ago

        Since they just removed memristors from The Machine, im thinking that HP will replace the memristors with this.

      • Den
      • 4 years ago

      You’d still have to find the location of data, but if it has at least x1000 faster access time (which I would assume is necessary if they plan to replace RAM that has nanosecond access times) then that hopefully wouldn’t be an issue.

      The biggest bottleneck could be getting the data to the GPU, although using nV link for consumer GPUs could probably help with that. So there would still be that loading for things that use GPUs and you’d still have to get the data to the CPU for everything. But if its x1000 faster, then 30 second load times would take 30 milliseconds or much less if access time and speed are both improved by x1000 (after all, if it could read/write 500GB/s then it would only take 20 milliseconds for 10GB to be transferred).

      • Generic
      • 4 years ago

      (squats on heapoverflow.com which, surprisingly, isn’t taken)

      • Laykun
      • 4 years ago

      Maybe, maybe not. You’ll still want some sort of file system structure for managing your data, and you’ll still probably want to load your file into memory (in this case, into the same memory system that the file is stored on) if you intend to do processing on it/make transient changes to it without effecting the original file. In the case that the file is to used un-modified you’d probably just use a memory mapped file, which already has existing APIs today and works with traditional storage systems.

      I think what’s going to fundamentally change is the kernel, and how it manages I/O, and most of these changes are going to be transparent to the application programmer/user.

    • HisDivineOrder
    • 4 years ago

    Hopefully, this isn’t one of those pipe dreams they often bring up to beat their chests on how awesome they are and is in fact an actual product that will make some meaningful difference.

    No, not like RDRAM. (Rambus, ptooey.) Like something useful.

      • DoomGuy64
      • 4 years ago

      Was Rambus actually bad, or was it the P4 it was paired with? I’m more inclined to say it was the P4.

        • NoOne ButMe
        • 4 years ago

        Rambus was better than Other RAMs in terms of performance (read Chuckula’s post below for a correction), but, it also costed 5-10x+ for the same amount. I believe. And, it was “faster” like how a 4.4ghz Ivy bridge is faster than a 4.5Ghz Sandy Bridge, nearly impossible to feel the difference in usage.

        It was terrible. Imagine if to use an Intel CPU you had to buy special RAM that had 20% faster transfer speed than [highest official supported DDR3] and fewer pins (I think RDRAM did have less) for only $200 for a 4GB stick!!

        Compared to, what. $25-30 for a 4GB DDR3? No clue what current DDR3 Prices are

          • chuckula
          • 4 years ago

          Rambus memory was actually slower in real-world use than the 100MHz and 133MHz SDRAM that was around at about the same time* due to massive latency that it incurred. The reason was that while RAMBUS did have higher theoretical aggregate bandwidth, it implemented a horrible serial protocol for actually doing reads and writes. Basically, the more memory you had, the longer reads and writes would take as the RAMBUS protocol moved data between the memory chips. In real-world use, SDRAM won in the vast majority of workloads.

          * This was just before the first generation of DDR1 came about and IIRC the chipsets that talked to the memory were mostly single-channel — then you trasnfered data over the FSB to the CPU.

            • TA152H
            • 4 years ago

            What you’re saying is inaccurate, and just common nonsense that gets handed down and repeated.

            RDRAM was a very good memory technology, the best of its time. But, it had to be used properly. What you’re referring to was not an issue with RDRAM, but with the systems it was initially used on.

            What was that? Pentium III. Which had a single-pumped memory bus running at 133 MHz. So, single channel RDRAM was already two times faster than the bus could handle, so the benefit was lost. With a single channel, which the 820 had, there was higher latency, making it generally slower than the overclocked 440BX, or even the 815.

            However, even on the terrible Pentium III memory bus, the i840 had very good performance using RDRAM. It would interleave memory, drastically lowering latency to the point where it was very competitive (would win some, would lose some) with the overclocked 440BX, and better than any other SDRAM solution.

            Also, DDR did not show ANY performance improvement over SDRAM on the Pentium III for the same reason – the system couldn’t use the extra bandwidth, and latency was not improved.

            When we move to the Pentium 4, which was designed for RDRAM, the entire situation changed. It was a poor processor, but hammered the K7 on memory performance. It also showed, on the aging i850, significantly better performance than Intel’s DDR solutions, even the second version which significantly improved performance. i850 was never enhanced, and still performed better.

            Ironically, Intel pushed RDRAM on the Pentium III so they could get volumes ramped for the Pentium 4, and the price would be competitive. It worked, for the Pentium 4, as the price was essentially the same as DDR and SDRAM, but the fiasco caused by it, and buggy Intel chipsets (i820 had to have a slot removed, both i820 and i840 had problems with the mth, used for using SDRAM for cost reasons), tarnished the image so much, Intel abandoned the memory when it was finally showing its value.

            But, contrary to misinformation spread around the web, Rambus was never the reason the memory was so expensive, as their royalty was quite low, nor was the memory inherently flawed. It was Intel’s stupidity to initially put it in a system that couldn’t possibly take advantage of the bandwidth, and then forcing it on people when it was too expensive. Because if they didn’t, no one would want it, since the platform couldn’t take advantage of it.

            • NoOne ButMe
            • 4 years ago

            Either no one could yield their memory or the fees were high. Choose one, or both I suppose if anyone is crazy.

            • yuhong
            • 4 years ago

            I think yield was a problem initially (remember PC600?), but testing RDRAM was a problem too.

            • Krogoth
            • 4 years ago

            RDRAM’s only caveats where that you need C-RIMM modules to occupy empty slots to complete a circuit and it ran rather warm since each memory cell in the module to have constant current (FYI, RDRAM was the first memory to use ramsinks that weren’t cosmetic).

            • green
            • 4 years ago

            which at the time meant to get the actual benefit out of rdram, your had to buy it in pairs
            at which point a lot of people were outraged at buying two when you could still buy individual ddr sticks
            fast-forward to today and buying a single stick of ram is a quite the rarity

            but overall the available bandwidth on initial systems was the downfall rdram
            it wasn’t until the “quad-pumped fsb” of p4 came around, with proper chipset, that the rdram came into it’s own
            as others have highlighted though, by then it was already too late
            kudos to amd at the time though who at time, from memory, had k7 going and bet on dual-channel ddr

            • chuckula
            • 4 years ago

            Dude, you’re wrong. I was there when the RAMBUS debacle took place and all the rose-tinted glasses in the world can’t compensate for the real issues that RDRAM had in the real world.

            If you had bothered to actually read my post, I pointed out that RDRAM had a higher theoretical bandwidth… but so what, it DIDN’T help in the real world because the gains in bandwidth were more than offset by the insane latency. Additionally, everything I said about their stupid serial protocol was dead-on right.

            [quote<]Compared to other contemporary standards, Rambus shows a significant increase in latency, heat output, manufacturing complexity, and cost. Because of the way Rambus designed RDRAM, RDRAM's die size is inherently larger than similar SDRAM chips. RDRAM's die size is larger because it is required to house the added interface and results in a 10-20 percent price premium at 16-megabit densities and adds about a 5 percent penalty at 64M.[1] PC-800 RDRAM operated with a latency of 45 ns, which was more latency than other comparable DRAM technologies of the time. RDRAM memory chips also put out significantly more heat than SDRAM chips, necessitating heatspreaders on all RIMM devices. RDRAM includes a memory controller on each memory chip, significantly increasing manufacturing complexity compared to SDRAM, which used a single memory controller located on the northbridge chipset. RDRAM was also two to three times the price of PC-133 SDRAM due to a combination of high manufacturing costs and high license fees.[citation needed] PC-2100 DDR SDRAM, introduced in 2000, operated with a clock rate of 133 MHz and delivered 2100 MB/s over a 64-bit bus using a 184-pin DIMM form factor. When more than one RIMM is installed on a memory channel, the performance impact is greater than for SDRAM because the data in the memory module furthest from the memory controller has to travel across all other memory chips, instead of just one or two chips in production SDRAM motherboards.[/quote<] [url<]https://en.wikipedia.org/wiki/RDRAM#Benchmarks[/url<]

            • blastdoor
            • 4 years ago

            Has anybody ever written a book, or blog post, or something, explaining how Intel went so far off the rails in the late 90 / early 00s? Rambus, Itanium, and Netburst — what the heck was in the water back then?

            • chuckula
            • 4 years ago

            You could say it was Intel being “innovative” when you remember that “innovative” actually just means “new” and doesn’t necessarily mean “better”.

            At least they hedged their bets enough to not try to put the whole company’s future on one particular [bad] idea.

            • blastdoor
            • 4 years ago

            Yes, they diversified their risk across multiple bad ideas 😉

            The fact that they had to license AMD’s implementation of 64 bit x86, and that it took so long for Core 2 Duo to come out, makes me think they had no plan B for the dynamic duo of Netburst and Itanium.

            They survived that era because of their massive manufacturing lead over AMD and because they were ultimately able to admit their mistakes and change course. There aren’t many companies that get to survive mistakes as bit as Netburst+Itanium.

        • Krogoth
        • 4 years ago

        RDRAM was designed for massive bandwidth throughput. It was far superior than DDR1 and SDRAM at the time, but the problem was that it first paired with Pentium 3 Coppermine that it was didn’t take advantage it and suffer from its higher latency. It wasn’t until P4 where RDRAM begin to shine. 850 and P4 were the optimal platform from Intel until 965/975 came along once Intel/RAMBUS exclusive deal expired.

        The main reason why RDRAM cost so much at the time was because the rest of the memory cartel refused to make RDRAM modules despite the fact that RAMBUS paid them to so. The memory cartel also sold SDRAM and DDR1 at a loss, but then again RAMBUS was pulling patent troll shenanigans over DDR1 tech.

        DDR2 and DDR3 incorporate some design cues from RDRAM.

      • seans665
      • 4 years ago

      They do actually have a real factory in Utah. I’m not sure how much difference it will make to the average user except reduced OS boot times. Technically it is a very big deal in terms of AI and robotics. I think it is something that will have more of a global impact in terms of increased automation in factories, reduced employment opportunities and so on. It could end up that you will go into a fast food joint and your order will be fulfilled by robotic arms. The cost of a robot for factory automation can be as low as $50,000. At some point humans just become uneconomical. There are going to be a lot of unemployed people and are they going to be provided for? The prevailing view point is that anyone who cannot provide for themselves can go to …..

    • mad_one
    • 4 years ago

    Thinking of your idea of using it for mobile as unified memory (twitter is a bit short for this):

    They are talking about 1000x the endurance of flash, which gives us a range of about 1M to 10M write cycles. Even with caching, you can get through that in a few hours in pathological cases, so wear leveling is needed.

    So how does it hold up with perfect wear leveling? I estimate ~1GB/s as average load for system memory, while the SOC is active. It will be more while gaming, probably less due to lots of idle phases when surfing the web.

    For a heavy user, the device would be active ~5 hours a day, 365 days a year. Heavy users exchange devices frequently, so let’s go with 3 years. This works out to ~20000 TB over the life time of the device.
    Assuming 64GB of memory, with 3M write cycles (basing it on current MLC*1000) and perfect wear leveling, we get 192000 TB endurance.

    So this may work, but it’s pretty close. Perfect wear leveling is not going to happen, since it has to be done in HW (maybe with a SW layer making adjustments based on HW counters for more advanced wear leveling) and needs to work at very high throughput, with random access patterns. At a guess, they’d need another order of magnitude on endurance.

      • mad_one
      • 4 years ago

      Thinking about this for another second, a DRAM cache large enough for the graphics buffers would almost certainly be enough to make it work. Would still give you a flat storage hierarchy and you could limit the cache to volatile data, if you want power outage protection.

        • Damage
        • 4 years ago

        Yeah, and a single DRAM stack near the SoC could act as a last-level cache for a system where 3D XPoint memory is the final stage of the hierarchy. This is all just speculation, but it’s hard not to think of the prospects. Tantalizing.

          • mad_one
          • 4 years ago

          We could finally see Android not being bogged down by bad memory management, devices with too little memory and poor storage performance.

          Seriously, every Android device I ever used was eventually upgraded because of this, never because of CPU/GPU performance.

          It will require a lot of changes in software to make full of a unified architecture. You still want to have seperate storage / working memory to some degree, so a software crash does not ruin the data.

          • Mr Bill
          • 4 years ago

          nevermind

      • Den
      • 4 years ago

      If its as conservative of an estimate as made by SSD manufactures, then >1 exabyte write endurance may be reasonable for mid-high end version of it after it matures a bit (basing that off the >1Pb write endurance of the 840 pro tested by techreport x1000).

      Also, if data is always kept in the memory (at least your primary programs and OS), then you might not need to write nearly as much as you do to transfer data to RAM (I’m assuming this is where your 1GB/s is coming from) – more than the increase in writes between now and when this technology is released. If it takes 10 years to get to market, then that 1GB/s could become 4GB/s (basing that on the shift from 1-2gb to 4-8gb as the norm in the last 10 years). Maybe more by the time the tech matures.

        • mad_one
        • 4 years ago

        Almost all the traffic is based on RAM traffic. Storage traffic will indeed go away, but I don’t think RAM traffic will change noticably. Since RAM traffic >> storage traffic, that won’t change much. It could help immensely with system performance, but that’s not the point I am discussing.

        Taking the 840 Pro, it has 256GB of Flash, rated for ~3000 cycles (I think, should be close anyway). With zero write amplification, as assumed above, this works out to 768TB. Assuming a write amplification of 1.5 the drive wrote 3.6 PB to flash memory, or ~14000 cycles. Which is quite impressive, however it may have failed the required retention duration before that point.

        Thus it exceeded the write cycles claimed for the flash about 4x. The reason the official endurance is dramatically lower than that, is the possibility of higher write amplification for certain workloads. And the desire to sell more enterprise drives.

        I don’t know enough about the physical properties of flash to estimate the effect of write cycles on retention.

          • Den
          • 4 years ago

          “Almost all the traffic is based on RAM traffic. Storage traffic will indeed go away, but I don’t think RAM traffic will change noticably. Since RAM traffic >> storage traffic”

          Isn’t a significant portion of RAM traffic just loading stuff from storage to RAM? I know some of that will go from RAM to CPU and back to the RAM and that won’t be effected. But if you did not need to load things into RAM, then that should decrease the writes on RAM significantly. Whether it be a 5% reduction or 90% reduction, I have no clue.

          ” it may have failed the required retention duration before that point.”

          If you assume that at the 600GB excluding WA was still functioning well (as it wasn’t reallocating sectors yet), then that’s probably about 1PB. So 250GB at x1000 endurance would be 1 exabyte. I forgot to divide by 4 to have for your 64GB example, which would by about 250PB of writes, which is pretty close to the 200PB you suggested – I thought you said 20PB, not 200PB. But like you said, it would only use 20PB over 30 years. About 70PB if you used 1GB/s 24hrs a day. Which means 9 years 24hrs a day would be possible.

            • mad_one
            • 4 years ago

            Maximum flash read performance on most phones is on the order of 100-300MB/s, while RAM is 5-10GB/s. Storage will be used heavily when you use more apps than you can keep in memory. Once you are using the app, storage will not be used much at all. The same is true for most PC applications. Unless you are talking servers, you don’t constantly access storage, which is a good thing, as storage was very slow until SSDs became a thing and it’s still poor on phones (writes especially).

            ” I thought you said 20PB, not 200PB”

            20PB is what I estimated you need, 200PB is what I estimated that 64GB of Micron’s new memory could endure. The main issue would be write amplification. SSDs are accessed in blocks of 512 bytes, vs random access for memory (though caches will still access it in blocks of ~64 bytes). Access time for main memory would be ~1000x lower than SSD access times (~100ns vs ~0,1ms), so there’s no way you can implement clever wear leveling in software. This has to be done in hardware and I don’t know how well they could do it and what the write amplicification would look like, but it’s going to be worse than what SSDs achieve (IIRC the TR test used a fairly benign access pattern for the endurance test).

            • Den
            • 4 years ago

            “Once you are using the app, storage will not be used much at all”

            But you also are not going to constantly be called by the CPU and edited and sent back to be wrote to the memory. Once its there, it may just sit there.

            “The main issue would be write amplification. SSDs are accessed in blocks of 512 bytes,”

            The article states “Intel also says the cross-point architecture allows smaller amounts of data to be written or read in each transaction than is common with NAND” but they don’t get any specific number so who knows what it would get.

            “Access time for main memory would be ~1000x lower than SSD access times (~100ns vs ~0,1ms), so there’s no way you can implement clever wear leveling in software.”

            If there’s a way you can reasonably tell what sectors have been used the most, you can avoid using them. Not sure why being faster would effect that.

            • mad_one
            • 4 years ago

            “But you also are not going to constantly be called by the CPU and edited and sent back to be wrote to the memory. Once its there, it may just sit there. ”

            Even if the application and OS do absolutely nothing, without panel self refresh you are going to read 8MB * 60fps = 480MB/s just for the front buffer. Do a simple animation and there will be 10s of MB per frame for compositing. With panel self refresh and no animations, you can get memory traffic very low, but that’s not as common of a situation.

            Decoding video, will result in 100s of MB of memory traffic per second, but very little disk traffic, even if that’s where you are reading the video from (it’s more likely to be streamed).

            “The article states “Intel also says the cross-point architecture allows smaller amounts of data to be written or read in each transaction than is common with NAND” but they don’t get any specific number so who knows what it would get.”

            This will help, but smaller accesses are possible and that makes it harder to do wear leveling.
            (I made a mistake in my previous post, you usually access disk data in 4KB blocks these days).

            “If there’s a way you can reasonably tell what sectors have been used the most, you can avoid using them. Not sure why being faster would effect that.”

            The difference is, that you need to make the wear leveling decisions faster (both higher throughput and lower latency). You can run a software routine with 100s or 1000s of instructions to decide where to place your data for an SSD. You can access thousands of bytes of RAM to make that decision. You can’t do that in this case (though you can do housekeeping periodically in software in the background, but a lof of the hard lifting needs to happen in fairly simple hardware).

            • Den
            • 4 years ago

            “read 8MB * 60fps = 480MB/s just for the front buffer”

            But reads wouldn’t matter. Self-refreshing shouldn’t be writing a ton either. Decoding and such would definitely.

            “(though you can do housekeeping periodically in software in the background,”

            That wouldn’t be able to do better than x10 wear difference between the most used and average used sectors during the early part of the lifespan compared to the perfect wear lifespan (~15 years with x2 WA)?

            • mad_one
            • 4 years ago

            “But reads wouldn’t matter. Self-refreshing shouldn’t be writing a ton either. Decoding and such would definitely. ”

            That is a good point. Considering this, my 1GB/s might be too much. I really messed up there. Not enough thinking.

            “That wouldn’t be able to do better than x10 wear difference between the most used and average used sectors during the early part of the lifespan compared to the perfect wear lifespan (~15 years with x2 WA)?”

            I think it should be better than 10x, so yes, it might work out. It’s still fairly close and needs a lot of research. Note that the DRAM cache suggested in an earlier post would likely take care of most problems, so it’s definitely doable.

            • Den
            • 4 years ago

            “I think it should be better than 10x, so yes, it might work out. It’s still fairly close and needs a lot of research.”

            Definitely too early to say much. If it were a difference of 5x though, it would still last about 6 years at 1GB/s (not including WA), 3 hours a day at x2 WA. I don’t think that would be good for marketing though even if only 1 in 100,000 would have an issue with the 3D Xpoint reaching its write limits before other parts breaking. So a cache good enough that they could honestly advertise that it could be used 24/7 for 5 years would be better for them.

    • ronch
    • 4 years ago

    Anyone here ever read about this tech some time ago on some tech website? I haven’t, although I have read some other articles about new memory tech that promise a revolution but to this day never made it to mass production and real-life relevance.

    This is how it’s done, folks. Just bring it out instead of talking about it but having nothing to show for it years and years later.

      • cynan
      • 4 years ago

      But they haven’t brought it out… At least not [i<]yet[/i<]. Vapor is still vapor only until it isn't.

        • nanoflower
        • 4 years ago

        True, but they say they will be sampling with customers in a few months. That makes it much more real than something that only exists in the lab and may be years before it ever gets to a customer in even sample form.

      • NoOne ButMe
      • 4 years ago

      Why the downvotes for you?
      They said sampling. The other people working on this promised to have working stuff in 2013 at first (HP) if I remember.

      IF they’re going to sample in a few months it means it has taped out good enough to work. In theory.

        • ronch
        • 4 years ago

        Don’t worry about the downvotes. More often than not, they don’t mean a thing. 🙂

          • blastdoor
          • 4 years ago

          I actually think more often than not, they mean people didn’t like a post.

          My impression is that upvotes mean the opposite.

    • NoOne ButMe
    • 4 years ago

    Well. It’s probably a great affordable solution for those spending tens of millions of dollars on hardware alone per year.

    Of course, if it isn’t, good. Still likely not not become competitive due to likely having higher retail, no matter the manufacturing costs.

    • CheetoPet
    • 4 years ago

    I just made the mistake of watching the presentation video ’cause for some crazy reason I thought there might be something vaguely technical in there. Stupid me.

      • chuckula
      • 4 years ago

      They didn’t call it an overclocker’s dream did they?

        • CheetoPet
        • 4 years ago

        Don’t think so, but their gaming usage examples caused me internal hemorrhaging. Shoulda just stuck with the enterprisey type usage.

      • Laykun
      • 4 years ago

      Saw two dudes in suits, closed the video.

    • anotherengineer
    • 4 years ago

    Insert “but will it play, load, etc. *your choice* faster” here

      • Srsly_Bro
      • 4 years ago

      will it load poorly disguised cliches faster?

    • chuckula
    • 4 years ago

    [quote<] Instead, it uses a property change of the memory cell materials itself. Furthermore, this property change uses all of the memory cell material. These innovations allow the memory cells to be shorter, packed tighter, and ultimately stacked higher, increasing density.[/quote<] Sounds an awful lot like phase-change RAM with a dose of 3D stacking for density. [Edit: The ability to address individual bits is a major step up over flash, that's for sure]

      • anotherengineer
      • 4 years ago

      Ya the stacking reminds me of HBM.

        • chuckula
        • 4 years ago

        I’d need to see more details, but it might be closer to the way that Samsung has implemented 3D NAND memory. That means the stacking is occuring in a single piece of silicon instead of being multiple dies that are stacked on top of each other (although both techniques could be combined together).

      • BryanC
      • 4 years ago

      Intel’s been hyping PCM for at least 15 years. I wonder what’s different this time.

        • chuckula
        • 4 years ago

        A working product at commercially viable densities doesn’t hurt.

          • BryanC
          • 4 years ago

          Is it at commercially viable density?

          The fact that they compared it to DRAM makes me suspicious.

            • Andrew Lauritzen
            • 4 years ago

            It’s smaller than NAND according to the article, and the first chips are 128Gb with possibility of stacking further in the future. Seems pretty good density 🙂

            • chuckula
            • 4 years ago

            128Gbit density is already commonly used for flash right now. 1 die gives 16GB of storage, and getting a relatively small device with 64 or 128GB of storage is probably quite doable, even if it costs around the same amount as what you’d expect to pay for a much larger traditional SSD. Say a 128GB device costs about $1000… not a problem if the performance is there (have you seen what 128GB of DRAM costs??)

            The comparisons to DRAM are:
            1. Comparing performance (where this stuff is slower than DRAM but not by a huge margin).
            2. Comparing price: Where this stuff is cheaper than DRAM.

            This memory is not intended to completely replace SSDs (at least at first). It is intended to provide a middle tier between traditional non-volatile storage and RAM.

      • guardianl
      • 4 years ago

      It’s phase-change (not that Intel/Micron are using the term). From BBC

      “By contrast, 3D XPoint works by changing the properties of the material that makes up its memory cells to either having a high resistance to electricity to represent a one or a low resistance to represent a zero”

      [url<]http://www.bbc.com/news/technology-33675734[/url<]

        • Waco
        • 4 years ago

        Sounds more like RRAM to me…there’s no mention of phase change here.

          • just brew it!
          • 4 years ago

          They don’t explicitly mention it by name, but the description of how it works matches what happens in PCM.

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