Don't call it Knots Landing: next Xeon Phi detailed

— 1:03 PM on August 27, 2015

Intel's sequel to Knight's Corner is more than just a fresh coat of paint. We've been hearing about the Xeon Phi successor for a while now, and the company released a torrent of new information at Hot Chips, detailed by Serve The Home.

Knights Landing-based Xeon Phis (Xeons Phi?) are built using tiles. A tile contains a pair of x86 cores based on the Silvermont microachitecture with customizations for HPC, which are fed by 1MB of L2 cache. Each core can track and execute four hardware threads. Within every core is a pair of vector processing units (totaling four per tile) that can be programmed using the AVX-512 instruction set extensions.

The Xeon Phi uses 36 of these tiles connected by a 2D mesh interconnect for a total of 72 cores, 144 VPUs, and 288 hardware threads. Intel then heaps on 16GB of on-package multi-channel DRAM (MCDRAM), which is Intel's high-bandwidth memory technology and not to be confused with AMD's HBM solution. The processor also has a six-channel DDR4-2400 memory controller for when 16GB isn't enough. 

Much like previous models in the family, Intel is pimping the Xeon Phi's x86 compatability as a big bonus over competing solutions like Nvidia's Tesla or AMD's FirePro compute cards. Multiple Xeon Phi processors can be strung together, talking to each other over PCI-express or the Omni-Path Architecture fabric

We already know about the US Department of Energy's supercomputer project. Now that the latest Xeon Phi family has been announced, we expecte more such projects will be on the way. 

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