Report: SK Hynix will start mass-producing HBM2 memory this year

A new generation of graphics cards is coming, and memory chipmaker SK Hynix wants to be part of the revolution. According to the German IT website Golem.de, SK Hynix plans to start production of second-generation High Bandwith Memory (HBM2) soon. 4GB SK Hynix chips are apparently slated for the third quarter of the year, and 8GB chips will arrive in the fourth quarter. With this move, SK Hynix provides some competition for Samsung, who already announced production plans for HBM2 memory.

This announcement follows standards body JEDEC's update of the HBM standard. HBM2 maintains the same bus width as HBM, but has higher clock rates and capacity. By increasing the frequency of a stack from 1 Ghz to 2 Ghz, the data rate can reach 256 GB/s, twice as much bandwidth as the earlier standard.

Golem.de reports that SK Hynix also has plans for slower HBM2 variants. Capable of 204 GB/s, these chips might be destined for future mid-to-low-range graphics cards, or for another application altogether. The site says that SK Hynix declined to specify whether the chips were intended for GPUs, SoCs, CPUs, or another application.

Comments closed
    • Tirk
    • 4 years ago

    So will the first GPU’s out this year be using Samsung’s HBM2 memory or will they have to wait for SK Hynix’s production to ramp up?

      • ImSpartacus
      • 4 years ago

      The very first new gpus will very possibly be using gddr5 and I’m not talking about rebrands.

      We’re not going to get a bottom to top hbm lineup in 2016. Probably not 2017 either.

      • Pwnstar
      • 4 years ago

      Samsung.

    • Srsly_Bro
    • 4 years ago

    So now I have to wait for this. I’ll have this 7950 forever at this rate.

      • HisDivineOrder
      • 4 years ago

      Could be worse. 😉

        • Srsly_Bro
        • 4 years ago

        Two 7950s?

          • ImSpartacus
          • 4 years ago

          [url<]http://i.imgur.com/EwLaDfI.gif[/url<]

      • albundy
      • 4 years ago

      ask your mom to double your allowance.

    • ImSpartacus
    • 4 years ago

    I very well could be in a derpy mood, but 4GB and 8GB chips sounds pretty high. Was that potentially 4GB/8GB packages (erm, stacks?) or maybe even 4Gb (0.5GB)/8Gb (1GB) chips?

    With hbm being made up of stacks of 4-8 chips, it can get confusing, lol. I haven’t read the source article yet.

    [quote<]4GB SK Hynix chips are apparently slated for the third quarter of the year, and 8GB chips will arrive in the fourth quarter.[/quote<]

      • cygnus1
      • 4 years ago

      Yeah, the “chips” they refer to are the stack of dies. So if Fiji had these 4GB chips, it would’ve had 16GB of ram total. I’m fairly sure that’s what we’ll see is 16GB of HBM2 memory for the top end, sometime this year or early next year.

        • ImSpartacus
        • 4 years ago

        Yeah, I just read the source article and it’s much clearer. We’re working with 8Gb (1GB) chips in stacks of 4, 8 and 2 chips/stack.

        So it looks like if we see hbm on Polaris 11, then it’ll likely only be two stacks initially (8GB of vram). Polaris 10 is probably still rolling with gddr5 for cost reasons.

        The Pascal side is much murkier. We’ll see what happens.

      • Pitabred
      • 4 years ago

      They are pretty high. May not be useful for GPUs, but for OpenCL/CUDA computing on server cards, that much memory with that much bandwidth would be a massive game changer of something that’s already crazy fast.

    • cmrcmk
    • 4 years ago

    If HBM(2) is using the same principles as POP SOCs, could this be used under something like a Xeon-D or would that add too much heat to the socket?
    Obviously all the Xeon’s pins would have to go through it but you might still be able to get 4 or 8 GB in one or two layers. This could either be main system RAM or a huge L4$!

      • ImSpartacus
      • 4 years ago

      Intel has its own hbm-like solution that will be implemented sorta like how you suggested. I forget the name. It’s a pretty dumb marketing name.

      It’s not quite hbm, but it’s similar.

      • cygnus1
      • 4 years ago

      it’s not really like PoP SOCs. There is an interposer layer that the cpu/gpu is attached to and the HBM stacks are placed around it on the interposer. they’re all on the same package, but the memory is not stacked on top of the cpu/gpu. think of the interposer like a little motherboard inside the SOC.

      [url<]https://techreport.com/review/28294/amd-high-bandwidth-memory-explained/3[/url<]

        • cmrcmk
        • 4 years ago

        I understand how it’s currently done. I’m wondering if anyone more familiar with the physics of chips could guess at how stacking the RAM under the CPU would work in practice.

    • the
    • 4 years ago

    The clock speed increase is a bit overkill compared to the HBM implementation we got in Fiji. The chip only ran the HBM memory at 500 MHz compared to the 1Ghz limit of the spec.

      • ImSpartacus
      • 4 years ago

      I think 14/16nm gpus will eventually grow to need the bandwidth (not initially, maybe in 2017 or onwards).

      Also, subsequent generations of vr will likely get truly ridiculous in the display dept. As well as retarded stuff like triple 5k monitors. We’re going to be dealing with a silly amount of pixels in a couple years.

    • RoxasForTheWin
    • 4 years ago

    Bring on Polaris and Pascal

    • DreadCthulhu
    • 4 years ago

    I wonder if this stuff will show up on Polaris or Pascal First.

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