Xeon E5-2600 v4 CPUs pave the way for the clouds of tomorrow

Intel released its Broadwell-EP Xeons today under the E5-2600 v4 umbrella. These chips include a number of features that virtualization-administrator readers may be interested in, including some fancy cache-management tools. The Broadwell-EP "tick" moves to a 14-nm fabrication process, and Intel has used this die shrink to increase core count while maintaining single-thread performance and holding the TDP line, according to Anandtech's review. Maximum supported DDR4 speeds also increase from 2133 MT/s to 2400 MT/s on some chips. The 22-core, 44-thread E5-2699 v4 is the king of this lineup, and it includes a massive 55MB of last-level cache. That's just one chip in the lineup, though.

Increasing core counts are amazing for virtualization density, but they aren't the sole limiting factor. In a virtualized environment, every resource is shared among guests, and the greater the granularity of control administrators have over those resources, the higher the potential for density. In modern VM environments, administrators have extensive control over most system resources, including processor frequency and core count, memory size, and disk I/O, among others.

With its Cache Monitoring and Allocation Technologies (CMT and CAT), Intel adds processor cache to the list of manageable resources. This system should prevent poorly-written or low-priority guests from taking more than their intended share of processor cache, allowing higher priority guests to make fewer memory calls and improve I/O performance.

CMT and CAT are part of Intel’s Resources Director Technology (RDT), which also adds memory bandwidth monitoring to its features today. The bulk of the new features serve as the foundation for fully-automated, software-defined infrastructures (or SDI). Intel says that the E5-2600 v4 chips are meant to allow businesses of all sizes to take advantage of SDI, not just large companies with huge public cloud infrastructures.

Broadwell-EP Xeons also get fully functional support for transactional memory using Intel's Transactional Synchronization Extensions, or TSX. Support for this feature was turned off in Haswell, Haswell-EP, and some Broadwell CPUs, thanks to an erratum that surfaced in August of 2014. Customers with Haswell-EP Xeons could use TSX for development purposes, but Intel only recommended that TSX be used on its Haswell-EX CPUs, which came to market as the Xeon E7 v3 family.

According to Anandtech, Broadwell-EP also brings some AVX performance improvements. On Haswell CPUs, mixing AVX and non-AVX workloads on the same CPU required all cores on the chip to reduce their maximum Turbo frequency to account for the increased power usage caused by AVX instructions. With Broadwell-EP, cores running AVX instructions will still clock down, but other cores will remain unaffected. Anandtech also notes that the PCLMULQDQ, or "carry-less multiplication" instruction now requires five cycles to complete rather than seven, and its throughput has been doubled. That's a boon for some cryptography-related tasks.


Tip: You can use the A/Z keys to walk threads.
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