AMD brings the Hammer down

AMD tooks the wraps off its upcoming Athlon successor, the "Hammer" architecture, at the Microprocessor Forum yesterday. See the press release if you like. As we've known for a while, the Hammer family will be capable of running standard, 32-bit x86 code, plus AMD's own 64-bit instruction set, which is intended as an extension of the existing x86 ISA.

Many of the rumors about Hammer are true, including the fact this eighth-generation design includes an integrated north bridge with a memory controller. (The memory controller supports DDR SDRAM in PC1600, PC2100, and PC2700 flavors). This design allows Hammer chips to work in tandem in up to eight-way multiprocessor configurations. The integration of the memory controller also ought to cut memory access latencies significantly. HyperTransport, AMD's high-speed bus and chip interconnect technology, figures prominently in the Hammer scene, serving as the bus that connects Hammer processors to each other and to the rest of the system.

Unlike Intel's Itanium, Hammer is aimed directly at replacing AMD's entire seventh generation (Athlon) product line. If all goes as planned, Hammer chips should appear everything from notebooks, desktops, and workstations to 8-way multiprocessor servers.

For more details, have a look at AMD's Hammer architecture presentation. There's a lot of info to absorb yet, so we'll try to keep you updated as the analyses pop up. As always, I recommend hitting JC's and Ace's to soak up all the juicy tidbits you can during events like the Microprocessor Forum.

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