Toshiba’s latest BiCS flash is stacked 64 layers high

Toshiba is stacking its 3D flash ever higher. In tandem with Western Digital (who now owns former Toshiba partner SanDisk), the company announced its third generation of BiCS flash chips today. These new TLC NAND devices maintain the same 256-gigabit capacity as their predecessors, but they stack those bits across 64 layers instead of the 48 in the last generation of BiCS flash. In time, the company expects to use this technology to deliver 512 gigabits (64GB) on a single chip.

On top of the expected density increase, stacking flash higher has other benefits. Toshiba says the technology reduces the cost per bit of flash and increases the amount of memory it can etch onto each wafer. Toshiba will make the new flash at its New Fab 2 facility in Yokkaichi, Japan. Samples of the new NAND are already on their way to manufacturers, and Toshiba expects mass production of BiCS 3 in the first half of next year.

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    • Waco
    • 3 years ago

    I’m more interested in “3D Super-NAND” from BeSang: [url<]http://www.eetimes.com/document.asp?doc_id=1330153[/url<] It can't be total snakeoil, and if the claims are even remotely true...this is disruptive, folks. HDDs are at ~3 cents/GB at best for SMR drives. EDIT: After some poking around, this might be just snake oil. Oh well. :/

      • iBend
      • 3 years ago

      but, when will it come true?

      normal SSD can reach that price in 3-4years

        • Waco
        • 3 years ago

        No, normal/3D NAND is only projected in the 10 cent range in 3-4 years. Source: Micron and SanDisk at MSST

    • Flying Fox
    • 3 years ago

    I am now more concerned with how much drop of write durability be for these new fancy configurations.

      • smilingcrow
      • 3 years ago

      Doesn’t 3D NAND use larger lithographic processes giving better durability?
      At least I think that is what Samsung quote for durability with the 850 Evo at least for warranty purposes.

        • xeridea
        • 3 years ago

        Yeah, they use larger process (don’t know what ones), since it is harder to stack them rather than laying flat to increase durability. In the end they still get better density due to the large amount of layers.

        • Wirko
        • 3 years ago

        It’s also possible that no one can make a chip with many 14nm layers today or in the near future. [url=http://www.extremetech.com/computing/193200-intels-14nm-broadwell-chip-reverse-engineered-reveals-impressive-finfets-13-layer-design<]Here[/url<] you can see how the 12th layer of Haswell looks like. Very, very coarse.

      • kuraegomon
      • 3 years ago

      In all likelihood, WD/Toshiba are using a process no smaller than 32nm for this flash. I think the previous Toshiba variant was 40 nm… but my google-fu was insufficient to confirm this.

      In fact, I seem to recall that most observers expected at least the first few generations of 3D NAND to stick with 40 nm.

        • smilingcrow
        • 3 years ago

        The link below suggests that it will stay at the current node for 15 years. Yikes!

        [url<]http://www.anandtech.com/show/10525/ten-year-anniversary-of-core-2-duo-and-conroe-moores-law-is-dead-long-live-moores-law/9[/url<]

          • kuraegomon
          • 3 years ago

          Yikes is right! Also, _80_ nm? I didn’t think I was _that_ far off on the process!

            • smilingcrow
            • 3 years ago

            I think it is 40nm but maybe they are using a different metric!

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