GlobalFoundries skips the 10-nm node on the way to 7-nm FinFETs

GlobalFoundries recently announced it would be adding a 12-nm node to its FD-SOI roadmap, and it's now announcing a more mainstream node for high-performance silicon: 7-nm FinFET. That move follows reports that the company would make exactly this move last month. Surprisingly, GloFo says it'll achieve this shrink using optical lithography alongside "EUV (extreme ultraviolet lithography) compatibility at key levels." The move to 7-nm transistors is claimed to offer 30% higher performance and two times more logic density compared to GlobalFoundries' 14-nm FinFET process.

The company also expects to re-use much of its existing 14-nm infrastructure to produce 7-nm parts at its Fab 8 campus in New York. Even with that re-use, GlobalFoundries will still invest billions of dollars in that plant to make 7-nm production possible. The expected payoff for GloFo is that it'll be able to begin 7-nm production more quickly than it otherwise might.

While one might be led to believe that GlobalFoundries is using the same silicon-germanium (SiGe) 7-nm technology that IBM showed off before it more or less paid GloFo to take its fabs off its hands, we're guessing that's not entirely the case. We've asked GlobalFoundries what the degree of overlap is between these technologies, and we'll update this article with more information if GloFo shares it.

GloFo says it'll continue its partnership with silicon design and intellectual property developer Invecas so potential customers will be able to get help building their products on the 7-nm FinFET process. The company claims that it's already making 7-nm test chips at Fab 8 with "IP from lead customers." "Customer design product starts" should begin in the second half of 2017, while a "ramp to risk production" is expected in early 2018.

Comments closed
    • everest333
    • 3 years ago

    “Surprisingly, GloFo says it’ll achieve this shrink using optical lithography alongside “EUV (extreme ultraviolet lithography) compatibility at key levels.”

    with EUV being a bit of a bust as regards getting the power levels up, isn’t it about time they invested long term in Proximity X-ray Lithography at 0.2 <>2.0 nm will be fine it seems given that EUV is using mirrors instead of lenses so the elementary collimating mirrors or diffractive lenses that are used in the place of the refractive lenses used in optics will also work there.

    OC the breakthroughs with new gamma ray Lithography Optics ,really Hard X-Ray, up to the Gamma-Ray range, with a wide range from negative to positive refraction seems logical even when you dont want to actually go that fine a mask etc…

    • techguy
    • 3 years ago

    7nm from GloFo in 2018? Don’t make me laugh. What’s the real average feature size of that process? 20nm? Intel is struggling to get sub 10. GloFo don’t stand a chance!

      • strangerguy
      • 3 years ago

      They learnt the best from the AMD parent: Roadmaps and hype and, when that fails to deliver, add more roadmaps and hype.

        • chuckula
        • 3 years ago

        When you’re a fanboy and you wanna go wheee….. but you ain’t got products yet.
        You hold on for your life.
        You hold on to your… roadmaps & hype.

        Roadmaps & Hype.
        Roadmaps & Hype.
        Roadmaps & Hype.

    • ronch
    • 3 years ago

    I wanna think all these foundries are finally catching up to Intel but all these newfangled fab process monikers are totally out of hand.

    A slap on the wrist is not nearly enough. A slap on the face and a kick in the nuts should be more effective.

    • rudimentary_lathe
    • 3 years ago

    I’m skipping the 7 figure salary and going right to the 8 figure salary in 2018.

      • davidbowser
      • 3 years ago

      Reminded me of “Best boss of you”

      [url<]https://youtu.be/VLPuI7cqX84[/url<]

    • ronch
    • 3 years ago

    They really can’t seem to get anything right below 28nm so it won’t surprise me if they end up licensing someone else’s 7nm.

    • melgross
    • 3 years ago

    Heh. Good luck to them. Right now, we know that Finfet doesn’t work at 7nm, and that the three technologies that are being looked at to replace it aren’t working yet either.

    How they can be so confident, I don’t understand.

      • Geonerd
      • 3 years ago

      Confidence is easy when “Proactively leveraging the synergistic potential of Dunning Kruger” is one of your company’s “core values.”

        • ronch
        • 3 years ago

        Core values are particularly important to microprocessor makers.

    • CScottG
    • 3 years ago

    “While one might be led to believe that GlobalFoundries is using the same silicon-germanium (SiGe) 7-nm technology that IBM showed off before it more or less paid GloFo to take its fabs off its hands, we’re guessing that’s not entirely the case.”

    Did IBM sell off their IP for 7-nm, or at least did they sell off the IP they thought was valuable for this node?

    Note: their contract with GloFlo was for production ABOVE 7 nm. My guess is that they paid to be rid of a lot of old technology and unprofitable contracts AND restrictions with the US government.

    I also wonder if purchasing their own stock wasn’t to meet some rules/restrictions regarding imports/exports for future manufacturing (..in addition to other factors.)

    -so maybe we get a SAP version of IBM for another half-decade, and perhaps then it’s back to hardware production in a manner that is profitable – globally.

    • basket687
    • 3 years ago

    “The move to 7-nm transistors is claimed to offer 30% higher performance and two times more logic density compared to GlobalFoundries’ 14-nm FinFET process.”

    Isn’t the 7 nm node supposed to be 4 times as dense as 14 nm? It looks like their “7 nm” node is more like a 10 nm node.

      • uwsalt
      • 3 years ago

      Yeah, I’m not quite sure what’s going on with that statement. They should be getting roughly quadruple density compared to 14nm.

      I’m inclined to say that it’s a typo or misstatement. While there is some fudge-factor in manufacturers’ quoted feature size at a given process technology node (e.g., not all “14nm” processes are created equal), it doesn’t make sense that GloFo’s 7nm would be no better than 10nm in terms of density.

      The question of whether to skip the 10nm node has been floating around for a while. Different manufacturers are reaching different decisions depending on their needs, customer base, and RnD plans. There’s no question that GloFo is skipping 10nm; their announcement that their process will incorporate EUVL is consistent with that.

      How successful they are in terms of getting the process working and getting decent yields out of it remains an open question. It was once thought that EUVL would be necessary sooner than 7nm to continue scaling feature sizes down. A combination of problems with implementing EUVL and some clever improvements to continue scaling with optical lithography pushed things off. Once again, however, the talk is that EUVL will be needed for 7nm; as indicated on industry roadmaps. We’ll see how things go this time.

        • jts888
        • 3 years ago

        It’s not a typo. As semiconductor fabbing improvements have become more difficult, the entire industry has kind of gone with a wink-and-nod agreement to just label incremental nodes with ≈1/√2 smaller numbers regardless of actual dimensions.

        The most notable and recent occurrence of this has been the 14/16nm nodes from GloFo/Samsung and TSMC, which really have roughly the feature dimensions of the 20/22nm processes but with FinFET structures instead of planar.

        My personal suspicion is that in GloFo parlance, 10nm would be an actual shrink and 7nm is the same shrink with some adjustments made. The ≈20nm planar nodes were pretty rough because of increased leakage, and a simple shrink of 14nm might be similarly underwhelming.

      • MathMan
      • 3 years ago

      The node size is little more than a marketing number. It has been like that for years now.

      The density is determined by more than just the gate length. You also have metal layer density, spacing rules etc.

        • NeelyCam
        • 3 years ago

        Node shrink used to mean about 50% more logic in the same area. TSMC 16nm didn’t offer much area shrink, but at least they offered FinFETs and higher performance/efficiency… so that’s still an upgrade.

        But what is GloFo offering here by skipping 10nm? One-node area shrink and one-node performance improvement? It would be like Intel calling their 22nm>14nm transition “22nm>10nm” transition.

      • melgross
      • 3 years ago

      Well, right now, only Intel has a true 14nm process anyway. Everyone else is using a much less dense technology.

        • NeelyCam
        • 3 years ago

        Is anything in that process [i<]truly[/i<] 14nm? Like Mathman said, node names are pretty much just marketing.

      • NeelyCam
      • 3 years ago

      I just logged in to post exactly this.

      It’s like “Hey, I have an awesome idea: let’s call our 10nm node ‘7nm(TM)’ node, so we can tell AMD that we’re ahead of Intel, and lock them into another wafer agreement!”

      • Mat3
      • 3 years ago

      Current “14nm” process is 14nm front end with 20nm back end. Sounds like those numbers are moving to 7 and 14 respectively.

    • Chrispy_
    • 3 years ago

    I remember reading back in the 65nm era that “Moore’s law is dead” and “there’s not much mileage left in die shrinking”

    Here we are discussing a die shrink that will have 86 higher density than the 65nm process that the naysayers were arguing was nearly the end of the line.

    If we can solve the heat generation issue, or find some snazzy way to cool them better, we’re going to see more vertical dies too with multiple stacked layers.

      • jts888
      • 3 years ago

      There’s a significant degree of truth to the naysayer line though.

      The 14/16 nm nodes really offer closer to a 2x density improvement over 28 nm instead of 4x.
      At this point the node names are more marketing than quantitative descriptions.

        • the
        • 3 years ago

        We’re in an era where scaling isn’t linear in terms of density. Quantum effects are starting to be necessary considerations for going further.

        It also didn’t help that TSMC’s 16 mm production was based upon there 20 mm line. The 16nm term is mostly for marketing purposes.

      • just brew it!
      • 3 years ago

      Yup. V-NAND seems to be working out well; it’s probably just a matter of time before we start stacking other types of chips.

        • the
        • 3 years ago

        TSV is possible with logic dies. The problem isn’t the concept but handling heat with several 100 W chips on top of each other.

        Until that is resolved stacking will remain isolated to low power chips and interposera.

          • Airmantharp
          • 3 years ago

          Just means that cooling systems will have to get a lot closer to the silicon.

      • tipoo
      • 3 years ago

      The 65nm era was about technical difficulties, but we’re now approaching the limits of how many silicon atoms will make up a switch. I think the march of progress will go on, but as you said, circumventing silicons limits with vertical stacking or moving to other materials rather than magically pushing past its hard lower limit.

      • Gadoran
      • 3 years ago

      In low power sub 5W SOCs definitively yes with TSMC doing a good job on this, but as the power goes up new advanced planar packaging solutions are better in future. The heat has to be dissipate in a short time and the vertical approach is a nightmare without a feasible solution.

      • WhatMeWorry
      • 3 years ago

      I believe the problem is that we are running out of positive integers.

      • MathMan
      • 3 years ago

      > Here we are discussing a die shrink that will have 86 higher density than the 65nm process that the naysayers were arguing was nearly the end of the line.

      86 higher density???

      Let’s do some math:

      GT200 65nm: 1.4 billion transistors, 576mm2 = 2.43 million transistors/mm2
      GP102 16nm: 12 billion transistors, 471mm2 = 25.5 million transistors/mm2

      Ratio: 10.5 high density.

      You’re off by an order of magnitude…

        • Chrispy_
        • 3 years ago

        I was taking 65×65 and dividing it by 7×7 to get 86x, that is all.

        The process may have an 86x density advantage; whether that advantage is fully exploited by chip designs on that process is another argument altogether.

          • MathMan
          • 3 years ago

          Yes, I know how you arrived at that number.

          And it’s completely wrong, because it assumes that density is determined by transistor gate size alone.

          It’s not. And there is no way for chip designs to exploit that.

            • Chrispy_
            • 3 years ago

            Okay, you’re right. No need to be harsh about it though.

            And being pedantic, [i<]I'm[/i<] the one who modelled my answer using math; What you did is compared two empirical values which isn't actually math.

            • Spunjji
            • 3 years ago

            Independent opinion: MathMan’s reply wasn’t harsh, it was direct.

            Being pedantic, it was applied mathematics that he used. So, math.

      • everest333
      • 3 years ago

      “If we can solve the heat generation issue, or find some snazzy way to cool them better, we’re going to see more vertical dies too with multiple stacked layers.”

      they can solve that heat generation issue already using Silicon photonics on package and on die, and OC High Speed Optical Interconnection Networks

      OC now you have the X-ray optics on a chip August 18, 2016
      [url<]http://phys.org/news/2016-08-x-ray-optics-chip.html[/url<] and OC there's also the latest in fabricating On-Chip Optical Memory

        • Waco
        • 3 years ago

        Silicon photonics aren’t going to help when stacking layers of compute blocks…

      • Coyote_ar
      • 3 years ago

      moore’s law IS dead. transistor count isnt doubling every 18 months.

      that doesnt mean that there wont be smaller processes and higher transistor count. its just that the rate slows down, and it did.

    • blastdoor
    • 3 years ago

    Regular unicorn cancelled, moving straight to magic unicorn.

      • TheMonkeyKing
      • 3 years ago

      I was thinking, sooner or later, they will get to a size where they have to split light into a spectrum (rainbows).

        • cheddarlump
        • 3 years ago

        That point happened 30 years ago.

          • GodsMadClown
          • 3 years ago

          Indeed, the extreme UV spectrum that is widely used for current lithography is no longer even part of the visible rainbow.

    • Gadoran
    • 3 years ago

    they said officially 7nm in 2020 a week ago, now 2018. Tomorrow they will say 2015.
    GloFo is a cartoon. I don’t trust anymore in this company.

      • Meadows
      • 3 years ago

      If you even just read the title, they’re skipping their 10 nm node for the express purpose of not having to wait until 2020 for 7 nm.

        • dodozoid
        • 3 years ago

        They simply rebranded their 10 nm node to 7 nm and BAM! INOVATION MUTHAFAKA!

          • Alexko
          • 3 years ago

          The density increase they claim is just 2×, so… yes.

      • everest333
      • 3 years ago

      what exactly do you need to trust them for!, do you run a line of chips there and need clarity…

    • chuckula
    • 3 years ago

    Just remember what happens to the best laid plans of meeses, men, and GloFo:

    [quote<]Although the move to FinFETs is something of a landmark transition, it comes in the form of an incremental step. GloFo's 14XM process will incorporate elements of 20LPM, building on it rather than supplanting it entirely. Like 20LPM, the 14XM process will include some double-patterning, and it will serve a range of devices from low-power mobile to high-performance computing. GloFo expects 14XM to go into production in the first half of 2014. Right now, the roadmap calls for another new process, 10XM, to come online the very next year, in 2015. The Alliance's work at 10 nm employs FinFETs and "second-generation" double-patterning.[/quote<] [url<]https://techreport.com/review/24343/ibm-globalfoundries-and-samsung-offer-a-glimpse-of-chipmaking-future[/url<] How well did all of that work out exactly?

    • ebomb808
    • 3 years ago

    Anybody know what “ramp to risk production” means?

      • flip-mode
      • 3 years ago

      Is that when you have Evel Knievel stunt-jump a Honda Goldwing over your production facility?

        • Convert
        • 3 years ago

        Thanks for the laugh this morning!

      • chuckula
      • 3 years ago

      Test chips being made in small batches for validation. Those test chips are by no means commercial products but are instead likely to be SRAMs or other simple devices that are made to analyze how well the process works.

        • uwsalt
        • 3 years ago

        Yep. There’s still a lot of work and time to put in before getting to commercial production of customer designs.

        I would add that they don’t specify what type of designs they expect to be start ramping into risk production in 2018. Initial test production doesn’t involve customer or complex designs. Usually that’s done with SRAMs, which are simple in design and uniform in layout. Those go through evaluation, test, and qualification. Then, depending on how things turned out, the process gets fixed (if needed), tweaked, and, possibly after more test runs, certified for running full customer designs. Then they’ll move on to test production with more complex or early customer designs. As before, that goes through evaluation, test, and qualification, which often leads to further process tweaks. Only then do they start looking at moving to full production of anything.

        • ronch
        • 3 years ago

        They should make chips the same way some companies cook potato chips : in small batches. All this mass production really kills their lithography. If only chips are hand made one by one, we’d be at 1nm already.

      • faramir
      • 3 years ago

      This is a euphemism for “add approximately one year to the date we just gave you to see when the very first products made using said technology will be available on the market”.

      • Chrispy_
      • 3 years ago

      “Risk wafer” is the name fabs give to the first batch of wafers to go through a new process.

      It takes 3-6 months to manufacture a modern chip, and that’s excluding all the design iternations, testing and engineering sample runs. Like, if you were to watch how an i7-6700K was made at Intel’s fab, you’d spend at least three months watching from the point when a silicon wafer was fed into one end and a wafer with hundreds of processor dies arrive out of the other end.

      It’s called “risk wafer” because it’s the first [b<]production[/b<] wafer that may end up being sold to customers, but it's also the guinea-pig for the fab. If there are teething troubles, the whole process is paused, the wafer might be scrapped, adjustments made and then the next wafer behind it in the queue will become the risk wafer. Because the process is so slow, there's no distinct "test run" for the whole process once a new chip design on a new node is ready to fab, so ramp to risk presumably means the ramp up to the first risk wafer start. If they get everything right first time, 3-6 months later you have a product, but then you have to add the time to correct problems and the losses of any scrapped risk wafers. Could easily be a year later before something hits a store shelf.

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