Samsung fires up 10-nm chip production

Half a year ago, Samsung announced that it was fabricating DRAM on a "10-nm class" process. Now, the company is announcing that it's fabricating microprocessors with 10-nm feature size—unspecified SoCs, more specifically. The company skips the vague "class" descriptor this time around, and says that it is using a new 10-nm FinFET process called 10LPE. This move is in contrast with GloFo's decision to skip 10nm and go straight to 7-nm manufacturing.

LPE, to delve into jargon for a moment, stands for Low-Power Early. Chipmakers usually use the term to describe a fabrication process that sacrifices some efficiency in exchange for a rapid time-to-market. Samsung didn't clarify exactly what SoCs it is manufacturing on the new process, but it did say that products based on the new parts will be launching early next year.

The company also says its upcoming second-generation 10LPP ("Low Power Plus") process will improve efficiency, netting increased performance while reducing power consumption. That upgrade is expected to begin mass production in the second half of next year, which coincides nicely with Samsung's expectations for its gargantuan new fab that it built last year.

Comments closed
    • JalaleenRumi
    • 3 years ago

    Specs would note:
    Huge Explosion and 10x more chance of no survivors.
    10x chance of spreading the fire
    Works best to be used in items that can be then used as C4s.

      • Krogoth
      • 3 years ago

      You are a big chip!

        • JalaleenRumi
        • 3 years ago

        But are you impressed?!

    • adisor19
    • 3 years ago

    If only they had a big customer to use all the production and bring in profits..

    Seriously though, on the last iPhone the TSMC fabbed A9 were more efficient even though they were made on a bigger node than the Samsung version of the A9. As much as Apple hates Samsung, they switched to TSMC for a reason and I doubt it was beacasue they wanted to hurt Samsung financially.

    Adi

    • jts888
    • 3 years ago

    [quote<]up to 30-percent increase in area efficiency[/quote<] Stupid me, I'd have guessed that going from "14" nm down to "10" nm would double area efficiency. At what point did lithography node names become complete marketing BS?

      • nanoflower
      • 3 years ago

      22NM? Seems like that’s at least when it became obvious the size label means little.

      • just brew it!
      • 3 years ago

      The node name only specifies the width of the narrowest feature. Component density hasn’t scaled with the square of the node size for a while now.

      • NeelyCam
      • 3 years ago

      Yeah, that’s like half-node scaling. Sort of like GloFo’s “we’re skipping 10nm to go straight to 7nm, but we’ll give you a regular single-node scaling benefit”

      The 40% power consumption reduction is pretty exciting, though.

      [quote<]" allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption."[/quote<]

    • chuckula
    • 3 years ago

    That title… you just had to, didn’t you?
    Not that I would have done it any differently.

      • Chrispy_
      • 3 years ago

      [quote<]sacrifices some efficiency in exchange for a rapid time-to-market[/quote<] So, explosive speed then?

        • nanoflower
        • 3 years ago

        The market is hot so they had to stoke the fires to get the products on the market.

      • Wirko
      • 3 years ago

      It’s a foundry, after all. The foundries that Google picture search shows me are all pretty well fired up.

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