AMD touts Zen die size advantage at ISSCC

AMD has had a tough time competing with Intel's CPUs over the last few years. The modular philosophy in AMD's construction-core processors could never find the type of integer-heavy parallel workloads it needed to shine. At the same time, Intel continually extended its consistent advantage in manufacturing technology every year, while pushing AMD out of the mobile and server markets almost entirely.

The red team claims it's now back and ready to compete in every CPU metric, including logic gate density. In a paper published as part of the International Solid-State Circuits Conference (ISSCC), the company claims that its Zen cores have a 10% advantage in die size compared to "Competitor A's" processor built on a 14-nm process.  EETimes' Rick Merritt says this is a reference to Intel's Skylake sixth-generation Core CPUs.

  Zen Competitor A
Tech 14nm 14nm
Cores 4 Cores, 8 Threads 4 Cores, 8 Threads
Area 44mm2 49mm2
L2 512KB, 1.5mm2 per core 256KB, 0.9mm2 per core
L3 8MB, 16mm2 8MB, 19.1mm2
CPP (nm) 78 70
Fin Pitch (nm) 48 42
1x Metal Pitch (nm) 64 52
Standard 6t SRAM (mm2) 0.0806 0.0588
Metal Layers 12 with MiM 13 with MiM

Table data: ISSCC via EETimes

A logic gate density advantage over Intel would be quite an impressive feat, but this news requires a little bit of seasoning. These figures come from AMD alone, since Intel doesn't release die size information. All of Intel's Skylake CPUs carry onboard graphics, but the IGP portion reportedly has not been counted in these measurements. Intel engineers may be the only persons truly capable of identifying exactly what parts of the die are specific to the IGP. Intel's die could also include logic for features like vPro that may not be present in Zen.

Smaller die sizes typically lead to cost savings for silicon manufacturers, though other factors also impact manufacturing costs. The fact that Intel runs its own manufacturing plants while AMD relies on third-party manufacturing from companies like Global Foundries and Samsung surely plays a role in determining AMD's production costs.

Merritt goes on to comment on the techniques AMD has reportedly employed to reduce Zen's switching capacitance by 15% when compared to existing chips. Zen is apparently the first design where AMD used metal-insulator-metal (MIM) capacitors, a move that's said to allow reduced processor voltage and more fine-grained control over per-core frequency and voltage.

AMD has claimed several times that Zen will compete toe-to-toe with Intel's desktop offerings when it comes to performance and power consumption. Now, the red team is saying that it is more than competitive with Intel with respect to silicon density. We can't wait to get Ryzen chips in the lab and tell you how AMD's latest squares up against Kaby Lake.

Comments closed
    • Klimax
    • 3 years ago

    I just realized why Zen core is smaller. It doesn’t have 256-bit units for AVX/AVX2. That might be why it is smaller. And incidentally it will cause in some corners quite problem for AMD. (For example in video processing. I am upgrading one of Avisynth filters and part of it is re-vectorization including support for AVX(2))

    Also Zen has fewer decoders. Those two might be biggest differences.

    • ptsant
    • 3 years ago

    So, everything points to a slightly smaller and less powerful core than Intel. I can’t imagine having better performance (in absolute) and less die size, especially given the Intel process advantage.

    I just hope we don’t get 8 anemic cores. That will hurt game benchmarks. All the rest points to a spectacular server CPU with great multi-threaded performance. Otherwise, I’m still sticking to my prediction of single-threaded performance competitive with the 6600K, not more. Which is not bad, by the way.

    • vargis14
    • 3 years ago

    I truly hope AMD has not lead us on in any way like they have so many times in the past.

    I also hope it is competitive and finally makes intel give us a real performance upgrade in the mainstream section Since my 2600k at 4848mhz is still pretty badass and PCIE 2.0 at 8x is yet to be a bottleneck at high resolutions, especially in the 1400p sector, let alone the 3440-1440 area IMHO

    • ronch
    • 3 years ago

    Back in the earlier days of computing chip companies commonly stated the transistor count of their chips. We still have them today but I think info on how many transistors a single CPU core has has become harder to come by. It would be interesting to compare the transistor counts of modern day cores to the ones we used to play Space Quest.

    • ronch
    • 3 years ago

    They’ve demonstrated performance and now they’re saying it’s also compact, which relates to manufacturing cost. Efficiency also seems to be better. Performance/watt/dollar, all bases covered. Is Zen gonna be the knockout punch that will send Intel to limbo? Heck, they’ll even license AMD GPU technology! Did I just wake up in the Twilight Zone??!

    It just worries me how those purported clock speeds from that Chinese source indicates somewhat low clock speeds. Are those fake? Is AMD being conservative? Is AMD leaving lots of clock speed headroom for OC nirvana? Is Zen’s IPC actually even higher to make up for lower clocks?

    • ronch
    • 3 years ago

    What a wonderful new lineup of CPUs! Intel is surely shaking in their boots.

    So exactly when will Ryzen come out?

      • chuckula
      • 3 years ago

      March 2, which is exactly 3 weeks from tomorrow (Feb. 9), if the purportations are true.

        • ronch
        • 3 years ago

        Purportations! Don’t you just love this word ‘purport’?? It’s like the shrimp in Forrest Gump!

      • freebird
      • 3 years ago

      Actually, this year, April 16 marks the date the when true “Savior” has “Risen”…
      Just saying…

    • Laykun
    • 3 years ago

    Even if AMD can’t actually make these CPUs perform well they have certainly mastered the art of pre-release hype, this is master class.

    • Shobai
    • 3 years ago

    All the talk of rumours piqued my interest, so I had a quick squiz; [url=http://www.digitaltrends.com/computing/amd-ryzen-desktop-cpu-listing-february/<]Digital Trends[/url<] gleaned from AMD's TaoBao listing , for a $295 4.2GHz Ryzen pre-order, that the shipping date would be the 28th of Feb. You're going to need to supply your own salt, of course.

      • tipoo
      • 3 years ago

      Unknown number of cores for that part leave value a complete question mark though.

        • Shobai
        • 3 years ago

        Absolutely! The interesting tidbit is, I think, the shipping date – it might shed some light on the “Buffalo.” situation… =P

    • Firestarter
    • 3 years ago

    I [i<]really[/i<] don't care, in fact I'd much rather have a large die than a small one, as long as I don't have to pay for it. Cooling these tiny little rectangles of fiery hot CPU power hasn't gotten any easier with their shrinkage

      • chµck
      • 3 years ago

      But smaller processes inherently generate less heat.

        • Shobai
        • 3 years ago

        The issue that Firestarter [fantastic, possibly ironic, handle choice there!] alludes to is the heat density, though. Overall the smaller process may indeed generate less heat [by what metric?], but that smaller process usually means a smaller physical area to dissipate heat through.

          • JustAnEngineer
          • 3 years ago

          [quote=”Shobai”<] Overall the smaller process may indeed generate less heat [by what metric?], but that smaller process usually means a smaller physical area to dissipate heat through.[/quote<] Energy in = Heat out. Power x time = energy. 91 watts = 91 joules per second = 310½ BTU per hour

            • Shobai
            • 3 years ago

            My apologies, I wasn’t as clear as I could have been. By metric I meant to ask ‘less heat than what, exactly?’. You’re right, energy in = heat out. Comparing leakage of a single transistor at different nodes isn’t terribly useful when the smaller node allows a designer to cram many more transistors into a smaller area – the task of appropriately cooling a heatsource becomes more difficult as area decreases.

      • tipoo
      • 3 years ago

      It normally would be a non-factor to most buyers, but doing more with less would allow them to respond to Intels inevitable pricing responses. For the survival of the company it should be encouraging, rather than them having to spend way more on die area to get not-2017-Intel performance.

    • DeadOfKnight
    • 3 years ago

    I thought Ryzen 4C/8T CPUs just had cores disabled? Are they saying it’s 2 different dies now?

      • chuckula
      • 3 years ago

      No. They are talking about an isolated measurement of one part of a chip, not the total die size of a product that you would actually buy.

      It’s like saying that a single core from a quad core chip is XX mm^2, but that measurement of a single core won’t change if you use the same core design in a chip with 8 cores or 16 cores (even as the size of the chip changes).

    • jts888
    • 3 years ago

    Before everyone goes nuts about AMD’s ostensibly superior cache design, remember that like every other form of engineering, ASIC design is a study in tradeoffs.

    At the very least, Zen’s per-clock cache bandwidth is half of that of post-Haswell Intel designs, including to L1D, between L1/L2, and between L2/L3. It’s possible to cut corners in other areas as well, such as using SECDED instead of DECTED protection on the SRAM arrays, etc.

    There’s just not enough data points yet to determine how much of the disparity is from low-level placement and routing choices, higher level feature/performance choices, or peculiarities in the different fab processes.

      • tipoo
      • 3 years ago

      Oh wow. After getting 5x the cache bandwidth of their last design, they’re still back by fully half?

        • jts888
        • 3 years ago

        Yeah, the bandwidth is only half, but there’s also the significant matter of necessity.
        Most non-SIMD integer workloads will be perfectly happy with 32B in/16B out per clock, but a 256b*2 AVX unit like in newer Intel designs would be completely hamstrung.

        I believe that Zen+ will adopt wider internal datapaths if and only if it adds wider AVX, but that’s an open question given future APUs like Raven Ridge and AMD’s hints at heterogeneous MCMs for servers.

          • Andrew Lauritzen
          • 3 years ago

          Right and it’s worth noting that the Intel comparison does have roughly double the SIMD throughput in that area, and presumably runs at higher frequencies as well if the rumors on that front are correct.

          None of this is to say that AMD hasn’t picked a good design point here (I believe they have), but just echoing the sentiment that it’s not as if this is a purely better design while taking less area or anything, as they would like people to infer 🙂

    • chuckula
    • 3 years ago

    [quote<]We can't wait to get Ryzen chips in the lab and tell you how AMD's latest squares up against Kaby Lake.[/quote<] Is that an anti-Buffalo statement there Wayne?

    • DPete27
    • 3 years ago

    It’s not the size that matters, it’s how you use it.

    • Anovoca
    • 3 years ago

    [quote<]like for features like [/quote<] and then like they tottaly like....

      • morphine
      • 3 years ago

      Um, like… I couldn’t even.

        • maxxcool
        • 3 years ago

        Like totally awaiting Leader952’s feedback on this article ..

      • tipoo
      • 3 years ago

      Like totally, for sure, I just got a Zenicure!

    • Tristan
    • 3 years ago

    new Intel cadence:
    tick, tock, Ryzen, Ryzen+, …

    • chuckula
    • 3 years ago

    This article from our pal Dave Kanter is from August but it was behind a paywall until a couple of days ago: [url<]http://www.linleygroup.com/mpr/article.php?id=11666[/url<]

      • cygnus1
      • 3 years ago

      Thanks for sharing that. Always love Kanter’s detailed writing.

      • AnotherReader
      • 3 years ago

      As always, it is a good read. There is a [url=http://www.realworldtech.com/forum/?threadid=164709&curpostid=164709<]related discussion thread at realworldtech[/url<].

      • ronch
      • 3 years ago

      Wow thanks!!

      • Klimax
      • 3 years ago

      And it effectively explains size delta. No 256-bit units and fewer decoders among other things.

    • Duct Tape Dude
    • 3 years ago

    Ryzen’s pre-release marketing is making me increasingly hopeful about the performance of these chips. Maybe they have most of it figured out. If Zen is even moderately competitive with Intel, it’ll be quite a success.

    I also imagine gen-2 Zens will improve performance with all the small optimizations they didn’t have time to refine because they’re launching an entirely new arch.

    The world is rooting for you, AMD!

      • ImSpartacus
      • 3 years ago

      But they did the same thing with Fiji (“great overclocker”,”slightly better than a 980 ti!”) and that stuff didn’t end up true.

      I mean, we’re all rooting for amd, but their track record isn’t very good when it comes to accurate marketing.

      I find it a little scary that the best metric amd thinks to use is die size. That’s kinda weird. If it’s better, show me more traditional benchmarks demonstrating that.

        • Duct Tape Dude
        • 3 years ago

        Totally true. AMD’s marketing is always pretty fluffy, and usually all we get are vague cherry-picked truncated benchmark bar charts instead of cold, hard, hardware specs. AMD has previously been left behind on physical characteristics, so comparing process-peens shows they’re finally in the same ballpark.

        They probably won’t crush Intel but it’ll be nice having second place in the same league again.

          • Klimax
          • 3 years ago

          Just hope die size isn’t the only thing good…

        • RAGEPRO
        • 3 years ago

        ISSCC isn’t a consumer event; it’s more for engineers to wave their junk around. This sort of announcement is more meaningful for other engineers and for investors, which is who it’s targeted at. I wouldn’t worry about it too much.

          • ImSpartacus
          • 3 years ago

          If it’s meant for engineers, then that’s almost worse.

          Laymen might not know how difficult it is to determine a pure “cpu-only” die size and all the potential “gaming” that can take place with making the choice to throw out or not throw out certain parts of the die. You could pull the wool over the eyes of a layman.

          But engineers? There’s no way they are chill with this half-assed die size comparison. They can smell the methodology issues a mile away.

          EDIT Fucking read the article. THIS IS AN ARTIFICIAL CPU-ONLY DIE SIZE MEASUREMENT. It IS NOT a simple “total” die size measurement that we’re used to. These are complicated SOCs with lots of stuff on the die. Intel does not disclosure which parts are and aren’t “cpu”. AMD is literally guessing what is and isn’t “cpu”.

            • Duct Tape Dude
            • 3 years ago

            Methodology issues? Do you suspect their Angstrom ruler was bent? They released physical measurements!

            • ImSpartacus
            • 3 years ago

            Am I the only one reading TR’s article? This IS NOT a simple die size measurement.

            [quote<]this news requires a little bit of seasoning. These figures come from AMD alone, since Intel doesn't release die size information. All of Intel's Skylake CPUs carry onboard graphics, but the IGP portion reportedly has not been counted in these measurements. Intel engineers may be the only persons truly capable of identifying exactly what parts of the die are specific to the IGP. Intel's die could also include logic for features like vPro that may not be present in Zen.[/quote<] Tell me, what IS a cpu core? Looking at a die shot, how do you determine what is and isn't part of the cpu? In today's world, these mobile parts are highly integrated SOCs. They're got a lot of stuff in there related to a ton of different tasks. In order to perform this silly exercise, a ton of assumptions need to be made as to what's what on Intel's die. Intel doesn't exactly tell you what does what on their die. It's absolutely frightening that the TR community doesn't see the insane methodology issues with this kind of thing, let alone AMD's abysmal track record with their marketing claims.

          • BurntMyBacon
          • 3 years ago

          I expect this comparison was made more for investors sake than anyone else. As you say ISSCC isn’t really a consumer event and they will have a very hard time convincing engineers that their comparison is beyond reproach. They can, however, convince investors that they are now in similar standing to Intel in one of the more critical cost associated metrics. While this is not enough information to determine how final costs compare to Intel, I doubt any any investors who saw this comparison came away feeling worse about their prospects.

      • Tristan
      • 3 years ago

      ryzens are already in some shops, waiting for release. Some unofficial benchmarks may start to appear soon.

        • chuckula
        • 3 years ago

        In fact, here’s an official R7 X1800X Pro in its retail box just begging to be purchased: [url<]http://i.imgur.com/FlFjCYB.jpg[/url<]

          • caconym
          • 3 years ago

          *sigh* just more sour grapes from intel fanboys

            • chuckula
            • 3 years ago

            I’d be careful calling California RyZens sour!
            They will go all claymation on you!

      • CScottG
      • 3 years ago

      I look at it just the opposite.

      It’s a very tenuous claim. When a competitor starts making reasonably feeble claims of being “better”, – you should start to doubt (or perhaps increase your skepticism) that the product actually is going to be better.

      What heightens my doubt is that it seems to be targeting the “street”.

      It’s effectively saying our manufacturing costs are going to be lower, while only looking at one aspect of production.

      Honestly, I hope I’m wrong – but to me this doesn’t bode well.

      (..and yes, I fully expect down-votes for being negative here.)

        • Duct Tape Dude
        • 3 years ago

        Right, but look who it’s from: AMD is notorious for fluffing up [i<]performance[/i<] claims based on questionable cherry-picked benchmarks, but here we have some hard numbers they'll at least be based on a similar process node instead of 1-2 generations behind (until Intel moves to 10nm, that is). All other claims aside, these measurements are less tenuous than usual for AMD.

          • ImSpartacus
          • 3 years ago

          These ARE NOT “hard measurements”.

          AMD is making a judgment call on which parts of Intel’s die are part of the “cpu”.

          Look at the stated sizes. They are in the 45-50mm2 size range.

          Now look at the size of an entire Skylake 4+2 die. It’s like 120mm2.

          [url<]http://www.anandtech.com/show/11083/the-intel-core-i3-7350k-60w-review[/url<] Something is being omitted to get down to 45-50mm2. AMD is not doing a simple "whole" die size measurement. They are picking which parts are "cpu" and which parts are "non-cpu". These are complex SOCs and Intel doesn't divulge what does what on their die. A judgement call is required to perform this analysis. I think TR did a fantastic job explaining how fuzzy these numbers could be: [quote<]this news requires a little bit of seasoning. These figures come from AMD alone, since Intel doesn't release die size information. All of Intel's Skylake CPUs carry onboard graphics, but the IGP portion reportedly has not been counted in these measurements. Intel engineers may be the only persons truly capable of identifying exactly what parts of the die are specific to the IGP. Intel's die could also include logic for features like vPro that may not be present in Zen.[/quote<]

      • UberGerbil
      • 3 years ago

      “pre-release marketing”
      You need to just stop there and think about what you’ve written.

      • ronch
      • 3 years ago

      I’ll probably get Zen 2.0. Maybe my board will kill itself by then so I would have a good reason for the wife to get new PC parts. You know, “I really don’t want to buy new PC parts yet but it just broke and I need my computer.”

        • JustAnEngineer
        • 3 years ago

        As much as I want to build a new system with Zen, I don’t have an excuse to do so at the moment. I’ll give it a hard look when I purchase a new graphics card later this year.

    • chuckula
    • 3 years ago

    Bear in mind that if you extrapolated Bulldozer/Piledriver’s die size based on the size of a 2-core “module” that they announced at ISSCC then Bulldozer should have been about the same size or smaller than a 4 core Sandy Bridge [both were made on 32nm processes that were roughly equivalent in transistor gate pitch].

    As you can see here, each 2-core module is 30.9 mm^2:
    [url<]https://www.pcper.com/reviews/Processors/Bulldozer-ISSCC-2011-Future-AMD-Processors?aid=1083[/url<] Multiply that by 4 for an 8 core chip, then factor in another 40% or so of the module size for the corresponding L3 cache, and tack on another 25 mm^2 or so for memory controller and hypertransport link and we get: 4 * 30.9 + 4 * 12.36 + 25 = 198 mm^2. Recall that a 4-core Sandy Bridge is 216mm^2, and the real size of Bulldozer was 315mm^2. Further remember that Bulldozer lacks many of the integrated features of more modern chips like the PCIe controller. Even if you think the memory controller size estimate is a little low, the module size from Bulldozer was certainly not indicative of the size of the final chip. [Yes, the closer we get to RyZen actually launching, the more that easily confirmable facts are frowned upon. I'm pretty sure there are going to be a lot of people pining for the 2016 neighborhood-of-make-believe version of RyZen instead of the 2017 version that actually launches.]

      • AnotherReader
      • 3 years ago

      At ISSC 2011, it was revealed that the [url=http://www.realworldtech.com/sandy-bridge-circuits/<]4 cores of SandyBridge, including the private L2 caches, take about 74 mm^2 of die space[/url<]. I am not sure about Bulldozer, but you might recall that the Pentium 4, despite being a narrower core than the K7, was much larger.

        • chuckula
        • 3 years ago

        Yes and… what exactly is that supposed to prove?

        I’m talking die sizes of real products, not announcements that are taken out of context by people on this site. Sandy Bridge as we all know was much much more than just its cores including the first truly integrated graphics processor that was released on a mainstream x86 desktop processor. For all of that, a full-bore 8 core Bulldozer should have still been smaller than the overall Sandy Bridge chip. It wasn’t, and that is a lesson that should be learned by people on here who are pretending that an 8 core RyZen is going to be the size of a notebook chip.

          • AnotherReader
          • 3 years ago

          It just shows that a Bulldozer module is substantially larger than a Sandy bridge core; therefore, the comparison isn’t apples to apples. However, your point about modern SOCs not being just about CPU cores is well put and the link in my previous post outlines just how much of SandyBridge was devoted to non-core functions. I’ll quote the relevant portion from the link:

          [quote<]The L3 cache and the bulk of the ring interconnect (which is on the same power plane as the cores) is 43mm2. The fully featured 12 shader GPU (called GT2) takes up 38mm2. The defeatured version (GT1) is about 55% of the size of the GT2 block. Some of the logic in the GPU, such as the ring stop (nearly 2mm2) and fixed function hardware cannot be removed in tandem with the shaders. The 18mm2 system agent includes the rest of the digital logic, including the DDR3 memory controller, a 20-lane PCI-E gen2 controller, the power management unit and display engines. Lastly, the physical layer interfaces for DDR and I/O comprise 12mm2 and 31mm2, respectively[/quote<] Edit: I am expecting the 8C Zen die to be substantially larger than Skylake based i7s, but then as you pointed out, that is hardly new.

            • chuckula
            • 3 years ago

            [quote<]It just shows that a Bulldozer module is substantially larger than a Sandy bridge core; [/quote<] Considering a Bulldozer module was supposed to be 2 cores + 2MB of L2 cache, it was [b<]supposed to be[/b<] larger. Furthermore, according to your own numbers 4 Bulldozer cores + 4 MB of L2 cache were still noticeably smaller (62 mm^2 vs. 74 mm^2) than 4 Sandy Bridge cores + a total of 1MB of L2 cache. We all know how that worked out.

            • AnotherReader
            • 3 years ago

            Ahem. 4 modules of Bulldozer require about 50 mm^2 more die space than 4 SandyBridge cores. The disparity in die size is much greater though.

            Incidentally, I upvoted your initial post, because it reminds us that cores aren’t the only consumers of die space.

      • ultima_trev
      • 3 years ago

      Seems to me all signs point to Haswell-like IPC but with AVX/FMA performance being closer to Ivy Bridge. Will still be good enough for 99% of consumers.

    • tipoo
    • 3 years ago

    It’s one thing for the core logic to be smaller, but I’m wondering how the same size L3 would be smaller when the fab still has fatter transistors than Intel. They’re (it and KL) both 16-way set associative too, right?

    Could just be a tuning of silicon for size over clock speed/other stuff, but Intels fab advantage seems pretty big to shrug off like that

    [url<]http://static1.gamespot.com/uploads/original/823/8237367/3060412-9679693880-Cell-.png[/url<]

      • RAGEPRO
      • 3 years ago

      Could simply be a more efficient layout.

      • Hattig
      • 3 years ago

      Intel’s 14nm can create dense transistors and SRAM cells, however higher metal layers are 1D layout, whereas GF’s 14nm has 2D layout. This undoubtedly improves overall density on the latter process.

      Regardless, for AMD to get 8MB of L3 in 16mm^2 compared to Intel’s 19mm^2 shows that processes aren’t just about measuring the base transistor size, but should consider full scale designs using those processes.

      We’ll never know internal costs of fabbing a wafer on either process, nor yield figures, etc, so it’s all just speculation, even when we do get some hard data.

      All we can really say here is that AMD appear to have done a good job on layout of a Ryzen CCX.

      • chuckula
      • 3 years ago

      Did anybody at AMD ever mention the clockspeed of those ultradense L3 caches?

        • AnotherReader
        • 3 years ago

        That is a good point. Optimizing for density versus optimizing for speed or power could explain the difference.

    • Voldenuit
    • 3 years ago

    Sizen confirmed.

      • tipoo
      • 3 years ago

      The only thing not Ryzen is die size.

        • NoOne ButMe
        • 3 years ago

        194* per Hans De Vries

        [url<]http://www.chip-architect.com/news/Zen_Summit_Ridge_First.jpg[/url<] Shot from earlier wafer shot shown. 194 based on the CCX being 44mm^2. Expect 8/12CU APU to be similar size, if not larger. 1 Polaris CU on 14nm is 4.25mm^2 based on fritzchens Franz on Flickr.

      • PrincipalSkinner
      • 3 years ago

      Performzen unknown.

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