AMD’s Naples platform prepares to take Zen into the datacenter

Now that the Zen core is out of the gate in consumer systems aboard Ryzen CPUs, AMD is launching its fight to retake data-center market share this morning with more details of the configurations and performance of its Naples server platform. The company is demonstrating Naples at the Open Compute Summit this week in Santa Clara, California.

Built around 32 of AMD's Zen cores, each Naples CPU offers 64 threads of compute capacity, eight memory channels, and 128 PCI Express 3.0 lanes from each socket. AMD says that in a two-socket configuration, a Naples server will offer more cores, more memory capacity, higher memory frequencies, and more PCIe lanes than a competing two-socket Intel server built around a pair of 22-core Xeon E5-2699A v4 CPUs.

In a two-socket configuration, Naples CPUs will devote 128 of their lanes of collective PCIe connectivity to AMD's Infinity Fabric interconnect. That still leaves 128 PCIe 3.0 lanes for connections to as many as 24 NVMe SSDs or other PCIe devices in a two-socket system. Among other benefits, AMD says the Infinity Fabric allows it to offer deterministic quality-of-service to VMs, establish roots of trust, perform secure boot operations, and more.

Specs are one thing, but everybody loves a good performance demonstration more. AMD pitted a Naples server against a two-socket Broadwell-E server with the same pair of Xeon E5-2699A v4 CPUs described above. The company chose a seismic analysis workload to demonstrate Naples' computing prowess, and the results seem promising. See for yourself in the following videos.

The first demonstration shows the Naples system running with 44 cores enabled, on par with the Broadwell-E system. Core for core, the Naples server completed this seismic analysis job in half the time needed by the Broadwell-E box.

With all 64 of its cores enabled, the Naples box shaved a few more seconds off its already commanding victory over the Broadwell-E system.

Finally, AMD increased the sample set size in its workload from one billion to four billion, at which point the Broadwell-E server couldn't even load the working set.

Another ideal use for Naples servers could be the creation of Radeon Instinct compute appliances. In a dual-socket Naples server, up to four Radeon Instinct cards per socket would each enjoy up to 16 lanes of PCIe 3.0 connectivity direct to the CPU. Those cards could then be used for applications like virtual desktop infrastructure delivery or machine-learning tasks.

We saw a Naples reference system along with the demonstrations above at AMD's Ryzen tech day just under two weeks ago. AMD says Naples servers will be available starting in the second quarter of this year.

Comments closed
    • ptsant
    • 2 years ago

    The fans are … scary. They look capable of driving a mid-sized plane to takeoff.

    • kc77
    • 3 years ago

    384/16 =24. The maximum memory speed on a 24 DIMM Xeon board with 16GB per stick is 1866 not 2400. Actually per the SuperMicro manual it should be less. I don’t know what board they used but it’s definitely not 2400. On server platforms the higher the capacity per stick the lower the speed. The more slots you fill also affect memory speed.

    The higher capacities come at a cost of performance and cost. Latency also increases as you add higher capacity DIMMS. 16GB per stick is usually the highest most people go because the cost per stick higher than that is outrageous as is the performance hit. More memory on this board would drop the speed even lower to 1600.

    What AMD is highlighting is that the 8 channel memory controller allows them to pack in more DIMMS without it affecting speed comparatively.

    • sophisticles
    • 3 years ago

    You can’t trust any test run by an interested party, AMD will always configure a test to show their product in the best possible light and Intel will always do the same.

    This test is obviously biased, the AMD slide claims that the Intel platform had 384GB ram and used slower ram (1866Mhz) but the provided link clearly shows that the Intel chips support up to 1.54Tb ram and 2400Mhz ram speeds; then AMD uses a data set that far exceeds the Intel platform’s installed memory and claims that as a win.

    So basically AMD took a memory bound test, used the fastest ram they could for their processor, used the slowest supported ram for the Intel processor, used significantly less ram for the Intel platform and then claimed the results as a win.

    And in typical TR fashion the article is written in a sensationalist fashion to make it look like AMD has something special (let’s not forget that TR’s founder went to work for AMD) AND the AMD faithful are all excited about another loser processor from AMD.

    What a shock.

      • Krogoth
      • 3 years ago

      You realize that platform that Broadwell-EP does not “officially” support 2400Mhz and enterprise segment is much more strict about following specs for verification? The Intel chips would have to use denser DIMMs(LRDIMM) but they are slower and much more expensive then standard registered DIMMs used in the match-up. It will still be “slower” in the test run then the Naples system.

      Broadwell-EP chips are being held back by dated Socket 2011 platform. The socket itself will become five years old later this year. It isn’t really that much of a surprise that Naples and its platform completely spank it. Naples is really meant go up against Skylake-EX and its re-vamped platform.

    • evilpaul
    • 3 years ago

    The important question: Are there any Task Manager screenshots?

      • Redocbew
      • 3 years ago

      How else are we going to know what’s going on in there? Seriously, what the hell.

    • Visigoth
    • 3 years ago

    Damn…this will be amazing for those of us in distributed computing. I can already see how many units of Seti@Home I’ll be able to crunch through! Hopefully the price will not be TOO much out there…

    • geekl33tgamer
    • 3 years ago

    I keep misreading it as “AMD Nipples”. Just thought I would put that out there…

      • Srsly_Bro
      • 3 years ago

      Someday you’ll be able to tell the two apart.

      sup?

    • cybot_x1024
    • 3 years ago

    this is all i could think of after looking at that 2U server with 32 DIMMs
    [url<]http://i2.kym-cdn.com/photos/images/original/000/461/903/3a9.png[/url<]

    • Solean
    • 3 years ago

    I hope AMD succeeds in this, if only to make a lot of money and become profitable again.
    That way, they might have money to spend on R&D for gaming CPU and GPU.

    • Krogoth
    • 3 years ago

    (Skylake-EX): Challenge Accepted

      • TheEldest
      • 3 years ago

      And dropped. Skylake EP will have fewer cores (28? max) and fewer PCIe slots (44 per socket?)

      If AMD can get the clockspeeds where they need to be for the 32-core part (>=2.0GHz) and have decent socket-to-socket and 8-core to 8-core performance they can knock this out of the park.

      Though I remember the pains that hypertransport had on the bulldozer opterons when they came out.

        • Waco
        • 3 years ago

        Or even the dual die Phenom II-based Opterons. They’ve had a long time (and many system deployments) to get that sorted out, so I’m optimistic. 🙂

        • jihadjoe
        • 3 years ago

        He said EX though, not EP.

        AFAIK Skylake EP (Xeon E5) will have up to 28 cores as you said. Skylake EX (Xeon E7) will have 32.

        • Klimax
        • 3 years ago

        They’ll have to upgrade massively core interconnect and parts of memory subsystem or those cores won’t be that much useful.

        See: [url<]https://www.techpowerup.com/231268/amds-ryzen-cache-analyzed-improvements-improveable-ccx-compromises[/url<]

          • Anonymous Coward
          • 3 years ago

          Well you saw the benchmarks, they weren’t too bad even in games. Apparently the big L3 is best viewed as being divided into halves, a bit like having two sockets or two dies in one socket. So for Naples, its a bit like having 8 bits of silicon sitting in one socket.

    • Kretschmer
    • 3 years ago

    Why doesn’t TR point out that there were discrepancies in the test system (e.g. memory configuration) that could be responsible for the reported results?

    I trust TR to do more than copy-paste press releases.

      • raddude9
      • 3 years ago

      They did, it’s right there in the 3rd image on the page, it would have been more obvious if they had not cropped the image though (which, among other things cropped out the words “Demo setup”), try here for the full image:

      [url<]http://hothardware.com/reviews/amd-poised-to-disrupt-the-data-center-with-zen-based-naples-platform?page=2[/url<]

        • Kretschmer
        • 3 years ago

        I meant verbiage that attributes the performance difference to multiple factors instead of “gee look at this AMD marketing video.”

          • nutjob2
          • 3 years ago

          Do you mean like that table right above the video that shows the Intel system has fewer cores, supports less memory channels, slower memory, and has fewer PCIe lanes? The Intel processor is less capable, clearly.

          Do you live in a country where thinking for yourself is forbidden? What verbiage do you need? Would this help? “AMD’s new product is crushing the competition.”

            • Waco
            • 3 years ago

            Is this where we pretend that 64 GB DIMMs don’t exist?

            EDIT: I should clarify. Number of DIMMs supported matters more than the number of memory channels. You can build Intel boxes with support for 96 DIMMs. How many does AMD support? At a guess, based on this design, it’s 64 DIMMs at most (4 sticks per memory channel).

            • Anonymous Coward
            • 3 years ago

            Perhaps you are saying that AMD should have thrown huge DIMMs at both platforms, and ended up where they started? Except poorer, and with slower memory.

            • Waco
            • 3 years ago

            I’m saying it’s a false comparison.

            • Anonymous Coward
            • 3 years ago

            AMD has more DIMMs, stop your crying.

            • chuckula
            • 3 years ago

            The same AMD marketing department employee who made sure the benchmarks for the 6900K were run in dual-channel mode because fairness should have done the exact same thing to make sure the Naples server ran in quad-channel mode because fairness.

            After all, isn’t fairness important?

            • Anonymous Coward
            • 3 years ago

            No. Does that hurt?

            • chuckula
            • 3 years ago

            Oh not in the slightest.

            I’ll be sure to remember that fairness is irrelevant the next time somebody whines about anything and everything that Nvidia or Intel does.

            In fact, even if my memory is crappy I don’t think I’ll have to wait that long.

            • Anonymous Coward
            • 3 years ago

            A surprising number of readers appear to have been born yesterday. Let this be the moment when you learned about marketing. Remember, from this moment forth, that people tend to present the facts in a way that favors their interests, if they bother with reality at all.

            • Waco
            • 3 years ago

            A surprising number of readers seem to not be in touch with technology, as well.

            • Anonymous Coward
            • 3 years ago

            Really, thats your argument?

            • Waco
            • 3 years ago

            Your argument is that AMD systems can hold more memory. This is provably false.

            What else do you have?

            • Anonymous Coward
            • 3 years ago

            Its hard to prove much of anything about Naples at this point, so watch out what you claim.

            One thing that can be proven is the memory channel comparison, which is 2-to-1 in AMD’s favor.

            • Waco
            • 3 years ago

            …on a particular platform, they have an advantage. Nobody is disputing that.

            • Krogoth
            • 3 years ago

            Do you have the white papers to back this claim up? Besides, Naples isn’t officially available yet and it is meant to go up against Skylake-EP and Skylake-EX not Broadwell-EP/Broadwell-EX.

            • Waco
            • 3 years ago

            Just AMD’s released info thus far. I don’t deny that against the equivalent 1P/2P Intel system, they have an edge.

            That edge doesn’t hold if you compare against the entire Intel lineup.

            I know I’ll be buying lots of Naples servers regardless, they can’t be available quickly enough.

            • Krogoth
            • 3 years ago

            It does hold-up simply because Socket 2011 shows its age when you scale-up more cores and sockets. Quad-channel DDR4 and QPI links on it don’t have enough bandwidth to go around when you dealing with 32 cores+ monsters.

            That’s why Intel is doing a complete revamp with their E5-E7 with Skylake EP/Skylake-EX chips. 😉

            • Waco
            • 3 years ago

            I’m not sure I agree with Naples having an edge over 4P boxes with E7 Xeons in anything other than price. 🙂

            • kc77
            • 3 years ago

            He’s correct. It really would help if the people here commenting had server experience.

            • Waco
            • 3 years ago

            More memory channels =/= more DIMMs.

            • Anonymous Coward
            • 3 years ago

            You’ll have a hard time winning this. AMD has twice the channels to play with. That means options AMD has to beat Intel in this test: throughput via more channels, capacity via more DIMMs, price via less dense DIMMs. There is simply no fair comparison because AMD has, in this challenge, beaten Intel. Move on.

            • Waco
            • 3 years ago

            Sure, you can build an Intel system that can’t hold as much memory.

            You can also build an Intel system with *far more* memory than the one shown here that is well in excess of what you can build on an AMD platform.

            What’s your point?

            • Anonymous Coward
            • 3 years ago

            I have a reply to that under the “maxxcool thread”.

            • nutjob2
            • 3 years ago

            What difference would that make? Those same 64GB DIMMs in the AMD system would still mean it has more memory. It burns when you realize that Intel has been playing for a rube, doesn’t it?

            • Waco
            • 3 years ago

            If you’re talking about a single DIMM per channel, sure, but AMD hasn’t exposed how many DIMMs per channel it can support. Do you really think they’re going to exceed the 12 TB servers you can buy today? That’d be in excess of 48 DIMMs per socket for AMD…

            Yes, I’m talking about E7 chips versus E5, but my point is that memory capacity is not lower on Intel systems, it is lower on SOME Intel systems.

            • Krogoth
            • 3 years ago

            That depends on what kind of DIMMs are you running. The Intel systems that have massive memory capacities have to use LRDIMMs.

            • Waco
            • 3 years ago

            Yep, that’s true.

    • Waco
    • 3 years ago

    Any word on major vendor releases? I asked HP and Dell recently, and they were mum. Q2 seems rather optimistic given that…unless the first OEMs will be junk like SuperMicro. 🙁

      • MOSFET
      • 3 years ago

      I see you’ve been playing against the full-court press today, but care to elaborate (even a bit) on your disdain for Supermicro? I’ve propped up some pretty junky low-end Dell servers before (broken IPMI, broken PSU redundancy even when not).

        • Waco
        • 3 years ago

        Even their best stuff has a failure rate far exceeding the norm. I’ve had the displeasure of working with their servers, JBODs, and power supplies in large quantities.

        When we approached them about the PSU failures that were outrageous, they (with the “they” being a very high ranking person at the company) responded by implying we were operating them out of spec (we weren’t) and wanted US to tell them what was wrong with them. Failing at rates many multiples of their competition wasn’t something they seemed all too concerned about.

        For everything other than PSUs (since as far as I can tell they’re pretty universally crappy):
        They’re fine for light use. They’re even fine for some medium use. Pushing them hard for extended periods of time reveals thermal issues, stability issues, etc.

        Dell has had issues, but in recent memory, they’ve been pretty damn good with the exception of their command line Linux idrac tools.

    • cmrcmk
    • 3 years ago

    Dang that’s a lot of RAM packed in there. We’ve got plenty of Intel servers with 24 DIMMs and those already seem physically dense. Until I saw the pic at the end with 32 DIMMs, I wasn’t sure it was physically possible in a 2U.

    • maxxcool
    • 3 years ago

    So THAT’s where the old marketing department when. Nice memory config ..

      • nutjob2
      • 3 years ago

      The Intel processor supports less memory. They’re maxing out the two systems with given sized DIMMs. The AMD system supports more memory, simple as that.

      I guess you want them to have the same sized memory to be fair. I also guess you want them to disable 10 cores on each AMD process too. And disable half the memory channels. And all those extra PCIe lanes the AMD has.

        • Waco
        • 3 years ago

        The Intel processors supports a hell of a lot more memory than used in the test.

        If they wanted to prove a point, it should have been versus a modern Intel box with 6 TB or more of DRAM. Oh, right, that wouldn’t be in AMD’s favor, now would it?

          • Anonymous Coward
          • 3 years ago

          So Intel has 6, then AMD has 8.

            • Waco
            • 3 years ago

            AMD has 8 memory channels, sure, but that’s not what we’re talking about here. Memory capacity isn’t just limited by channels, it’s limited by what the memory controller can support. AMD hasn’t explicitly stated how many DIMMs per channel it can support, so playing stupid games by limiting one system and not another is just that…a stupid game.

            I can build a system today with 12 TB of RAM. I’d be surprised if AMD is going to support more than 48 DIMMs per socket…

            • Anonymous Coward
            • 3 years ago

            If you dig up some obscenely expensive Intel box supporting the world’s most massive DIMMs, then AMD scores an easy win by playing around with only 1TB or so of data with their higher bandwidth and lower latency “mainstream” DIMMs. Then they throw in a slide comparing prices of the systems, and people like yourself go ape because its not fair.

            This is so easy for AMD to win, they have options at their disposal.

            • Waco
            • 3 years ago

            People like me? Jesus, get your combative bias out of here, it’s obnoxious and unneeded.

            I want Naples to be awesome. I want them to drive down prices on Intel systems.

            I’m not, however, delusional enough to play stupid games like “AMD is better because it supports less memory” or “AMD is better simply because it is cheaper” or “Intel is stupid because they cost more while being more capable”.

            They can’t play the “we support more DRAM” game…when they don’t.

            • Anonymous Coward
            • 3 years ago

            This thread is full of people screaming unfair, including you, currently you’re excited about max memory capacity but in order for Intel to bring out that huge memory capacity (which might in any case still not beat AMD, depends on specific motherboard and what DIMMs get approved) they would need to sacrifice performance and/or price, which is simply another avenue for AMD to claim victory. AMD could have done that to their Intel test box on purpose, just to make it loose worse and simultaneously be super-expensive.

            More channels is more options. In this case, more DIMMs and more bandwidth.

            • Waco
            • 3 years ago

            I didn’t scream unfair, I said that the test that emphasized lack of memory was unfair. It is.

            • Anonymous Coward
            • 3 years ago

            They didn’t compare performance to one Intel box and capacity to another, they used the same box, they beat it on both performance and capacity. That is perfectly fair.

            • Waco
            • 3 years ago

            I can’t tell what you’re arguing here. They compared to an incomparable server for that workload. You don’t test something that literally can’t be run on one versus another and call it a fair comparison…

            Now if they’d emphasized price, or something, that had a hard cap on how much memory you could buy and what Intel CPUs were in play (since the idea is that Naples boxes are cheaper, right?) then they’d at least have some validity to the stunt.

            • Anonymous Coward
            • 3 years ago

            AMD showed their box winning on performance and capacity. I guess you’re upset that they demonstrated capacity by having processing fail on the Intel box.

            • Redocbew
            • 3 years ago

            HPC isn’t my field, but isn’t “winning” based on memory capacity of a single server a bit of a hollow victory? If you need more shouldn’t it be possible just to add another server?

            • Waco
            • 3 years ago

            Ugh. You’re just being intentionally obtuse.

            I’m not upset. I think the comparison is stupid. I’m glad AMD won, and I plan to buy lots of their hardware when it is available.

            You seem to continue to try to paint me as an anti-AMD and pro-Intel fanboy. I am neither; I am objective in my assessment and it will be best for [i<]everyone[/i<] if AMD succeeds with flying colors. These trite comparisons don't help them, though, and that's what annoys me.

            • Anonymous Coward
            • 3 years ago

            My point is that AMD made a perfectly valid marketing presentation in which their platform outperformed Intel on both memory throughput and memory capacity. I assert that is was perfectly valid for the AMD machine to have more RAM, since it had more slots and more channels for said RAM. I assert that it does not enhance validity to talk about Intel machines that can support more memory than used in the AMD demo, because such configurations reduce memory performance and increase price in a way that was favorable for AMD’s marketing. (As it is, I suspect the amount of RAM in the Intel box probably reduced bandwidth, 3 DIMMs per channel vs 2 for the AMD box.) I assert that AMD’s position is superior, or more correctly will be superior with Naples, when it comes to possible memory configurations, by which I am referring to some user-defined combination of throughput, price and capacity.

            • Waco
            • 3 years ago

            If you say so. I disagree that Naples will compete with 4P boxes from Intel. It may very well shake up the market considerably for 1P/2P boxes, and I hope it succeeds at that.

          • nutjob2
          • 3 years ago

          So does the AMD box, even more than the Intel. AMD is making a mokery of Intel and its fanbois.

            • Waco
            • 3 years ago

            Fanbois? I surely hope you’re not thinking I’m a fanboy for being critical of marketing stunts.

            RAM channels =/= RAM capacity

            • nutjob2
            • 3 years ago

            Nope, but AMD will support a sane number of DIMMs per channel and still beat Intel in capacity, becuase it has twice as many channels, thus better performance, you know, that thing you’re actually paying for.

            But when it comes to HPC, if you don’t have channels then you just have contention on the memory channel. So I guess you’re saying Intel having more DIMMs per channel in lieu of extra channels is some sort of benefit? LOL!

            You’re absolutely clueless about how computers are engineered, but keep posting, I’m getting a good laugh out of you.

            • Waco
            • 3 years ago

            In this specific AMD versus E5 Intel CPUs, they have an advantage.

            Keep assuming things and trying to make this a “me versus AMD” thing if you like, but I would wager I deal with HPC and systems design a lot more than you do, considering [i<]it's my day job[/i<].

        • maxxcool
        • 3 years ago

        Oh, when you take a Audi v10 to a race YOU disable 4 cylinders to compete with Subies ?? /riiighT/.

    • AnotherReader
    • 3 years ago

    Any word on base clocks for the 32 core system? Is this based on another die (16 core) or are they using a 4 die MCM?

      • Waco
      • 3 years ago

      4 die MCM, hence the 8 memory channels. I’ve heard rumors of a Naples platform with HBM embedded on an interposer as well…

        • AnotherReader
        • 3 years ago

        Pity. Two 16 core dies would have been better from a performance point of view. Going out of the 16 MB of L3 for each 8 core die will hurt. However, I expect that scheduler changes will mitigate that.

          • Waco
          • 3 years ago

          Multi NUMA-node stuff on previous AMD chips hasn’t been too terrible with a little optimization of device scheduling. It’s going to be similar to the prior Magny-Cours chips, in that a 2P box has multiple sets of NUMA domains, however, this is more simple (it’s just in-socket and out of socket, versus the older model of in-socket, near socket, and far socket).

            • AnotherReader
            • 3 years ago

            That is better. Let’s hope that the cache coherency protocol has been overhauled too.

        • jts888
        • 3 years ago

        I think AMD’s intentions to make Zeppelin+Vega MCM APUs for enterprise is a pretty open secret. There have been R&D presentation slides floating around for years, and they’ve made a big production out of the fact that Vega and Zen are both built around their new Infinity Fabric interconnect.

        • AnotherReader
        • 3 years ago

        If that is the case, then each Ryzen Die should have 32 PCIe lanes. We don’t see that for AM4; perhaps they are disabled.

          • Waco
          • 3 years ago

          They are disabled from what I can tell. It’s exceedingly confusing knowing that there are parts of the die there that just aren’t routed to the socket…

            • AnotherReader
            • 3 years ago

            It would have been nice to have 32 PCIe lanes on a normal desktop.

            • jts888
            • 3 years ago

            Is it confirmed that a 1S platform wouldn’t support all 128 lanes, since IF wouldn’t be needed? The first pic above seems to suggest the possibility at least.

            [b<]Edit: [/b<] nevermind, actually tried reading the article. Looks line the PCIe PHY lanes are being dual purposed for the inter-socket IF stuff, which makes some degree of sense to me.

            • Waco
            • 3 years ago

            I was hoping they would do that, but I wouldn’t imagine they’d build 2 socket types if they didn’t have to.

            I’d LOVE a 1 socket 128 lane PCIe solution, even if memory bandwidth might become an issue.

            • jts888
            • 3 years ago

            I think 2S is more about doubling aggregate memory bandwidth and having higher thermal/power headroom than anything else. I’m sure the PCB layers in Naples are already a nightmarish maze, and I can’t begin to imagine having 6 or 8 DDR4 channels hanging off each side of a 48 or 64 core mega-MCM.

            What kind of use case scenario are you envisioning for 1S PCIe x128 though? I imagine heavier Naples builds being 1U 2S with 10 u.2 NVMe drives, 40 Gb networking, which doesn’t really begin to strain the PCIe lane budget. It’s also not realistic to squeeze in more than 2 GPUs per U, so I guess my imagination is lacking here.

            • chuckula
            • 3 years ago

            I think Waco wants to use PCIe cables to hook the board up to external devices.
            Otherwise there’s no real practical way to actually use all 128 lanes on a single motherboard.

            • Waco
            • 3 years ago

            Actually, no. 😛

            There were some cool PCIe network topologies in the works a few years ago but they were snuffed out.

            128 lanes is only 8 slots of x16 bandwidth. There are *plenty* of applications for IO servers that are lane-starved at the moment to utilize that many lanes in HPC environments. I find that I am typically PCIe lane starved long before I’m ever CPU or memory limited when dealing with Intel servers. I’d love to be the other way around, as it drives both efficient software and much smaller networks (in terms of node count).

            Offhand, I’d like to be able to build a node with 40 GB/s of bandwidth that bridges two networks (Lustre routing). I’d also love to be able to build a storage box with 4 or 6 quad-port SAS cards and 2-3 100 Gbps IB cards…

            Long story short, there are many IO applications in the high-bandwidth world.

            • chuckula
            • 3 years ago

            Interesting. If you can cram all the cards into the box then go for it.

            • brucethemoose
            • 3 years ago

            Is that still true if you can’t use everything at once? A 1P or 2P Naples server only has 64 lanes running into/out of the CPUs themself, AFAIK.

            • Waco
            • 3 years ago

            I’m not sure what you mean – a 2P Naples box has 128 lanes of PCIe. My hope was for a 1P box with 128 lanes, but they aren’t building those (they have not announced it, anyway).

            • brucethemoose
            • 3 years ago

            From the Anand article:

            [quote<] In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD’s Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again. ... However, each die only has 16 PCIe 3.0 lanes (24 if you want to count PCH/NVMe), meaning that some form of mux/demux, PCIe switch, or accelerated interface is being used. This could be extra silicon on package, given AMD’s approach of a single die variant of its Zen design to this point[/quote<] In other words: At most, you get 16 (+ 8 for the chipset) lanes out of each Ryzen die. Naples is just 4 of those Ryzen chips glued together, and apparently 1/2 those PCIe lanes are used for the interconnect in a 2P system. So the math doesn't add up... AMD is either using an enormous PCIe switch on each MCM, they're using a different die, or there are a bunch of disabled PCIe lanes on the current chips. The last 2 seem pretty unlikely.

            • jts888
            • 3 years ago

            Each Zeppelin die has 32 PCIe 3.0 lanes, with 8 reserved for the chipset and 24 available on the Ryzen platform.

            It turns out that Zeppelin can repurpose PCIe lanes as inter-socket interconnect lanes, which is a good way to conserve die space assuming that:[list<] [*<] customers don't need IO to scale with socket count and that 128 lanes is good enough for 99.99+% of people [/*<][*<] 2S is enough, since fully connected 4S needs 3x the links of 2S [/*<] [/list<] Beyond that, there is some sort of also as-of-yet undisclosed Infinity Fabric link on Zeppelin for MCM/interposer-only links, which can be a lot denser and lower power because of the tighter signal strength guarantees. I don't think there's currently anything here that blatantly doesn't add up.

            • brucethemoose
            • 3 years ago

            Source?

            Everything I see (including TR’s articles and this LegitReviews article on the subject: [url<]http://www.legitreviews.com/amd-ryzen-learned-ces-2017_190305[/url<] ) indicates 16 + 8 for the chipset. That sounds like a plausible explanation though.

            • jts888
            • 3 years ago

            Sorry, I only have the word of some better informed colleagues.

            While there may actually still be a few unused lanes on a given board, most of the apparent lane deficit is just eaten up by mundane stuff like controllers for GbE, onboard audio, extra USB controllers, etc.

            Why use the processor’s precious PCIe 3.0 lanes and not just the chipset’s 2.0 lanes for this kind of garbage you might reasonably ask? Just simpler mobo trace layouts.

            • Waco
            • 3 years ago

            Source? AMD itself says the die has 32 lanes.

            • Waco
            • 3 years ago

            There are a bunch of PCIe lanes that aren’t active on the current chips on desktop sockets.

            EDIT: THIS IS WRONG. DO NOT LISTEN TO ME. 🙂

            EDIT2: Also, Anand is wrong. There are absolutely 32 lanes per die.

            • jts888
            • 3 years ago

            That doesn’t sound right to me. A Ryzen processor has 32 PCIe 3.0 lanes, with 24 available to add-in peripherals and 8 (I would assume) being used by the X370/B350/A320/A300 chipset.

            Since the chipsets can expose up to 8 PCIe 2.0 lanes in addition to a bunch of SATA and USB ports, I feel pretty safe in my assumption that 8 3.0 lanes are both needed and used.

            • Waco
            • 3 years ago

            I was wrong – you’re right. There are 24 lanes for use, and 8 more used for southbridge + IO.

            • jts888
            • 3 years ago

            Where did you hear that there definitely won’t be?

            I would have assumed that this would be a choice left to mobo vendors and that the IO pins on the socket could be used as either peripheral or processor interconnect lanes.

            • Waco
            • 3 years ago

            I didn’t hear definitely, but I haven’t heard anything about 128 lanes from a single socket from anyone except that single AMD slide.

            I’d love to be wrong. 🙂

      • freebird
      • 3 years ago

      previously in some articles months ago, Naples was listed at 1.4Ghz boosting to 2.8 or 2.9Ghz. Probably needed to make them low to keep four Ryzen CPUs under the TDP listed which I can’t recall…

      Here’s a link:
      [url<]http://wccftech.com/amd-zen-naples-32-core-cpu-benchmarks-leaked/[/url<]

        • AnotherReader
        • 3 years ago

        That seems too low. I would expect base clocks close to 2 GHz.

        • Anonymous Coward
        • 3 years ago

        Is there any particular reason that AMD couldn’t push insane wattage through these things? Perhaps power delivery into the package, and a limit on how physically large the heatsink in a size-constrained server can be. Thermal density on the silicon itself would not be a problem, and they can sort and package together dies with comparable clock speed potential.

        If they can do 8 cores at 3ghz on 65W, I’m thinking they could get 32 cores at 1.4ghz into 65W as well.

    • JosiahBradley
    • 3 years ago

    Totally want these for new Hyper V boxes with hyper converged NVMe. This would make a killer VM node.

    • Tristan
    • 3 years ago

    2x faster in quakebench 🙂

    • chuckula
    • 3 years ago

    [quote<]The company chose a seismic analysis workload to demonstrate Naples' computing prowess, and the results seem promising. See for yourself in the following videos.[/quote<] Is this "seismic analysis workload" available to the public? [Yes, downthumbs from AMD fanboys who don't want to run AMD's own favored benchmarks on their own RyZen rigs. It's funny how AMD fanboys don't want to see a benchmark where [i<]purportedly[/i<] the lowest-end RyZen 1700 ought to be a solid 70% faster than the 6950X and double the speed of the 6900K. Instead of wins like that, they want to focus on a 5% lead in Cinebench?]

      • Wirko
      • 3 years ago

      Yes, on one condition. Your permanent address must be in the Pacific Ring of Fire.

      • Concupiscence
      • 3 years ago

      It’s not hard to find [i<]a[/i<] workload, and AMD probably used something publicly available... Heck, it could easily be a synthetic dataset knocked together by some grad student and made publicly available. God knows they wouldn't try to license proprietary data to that end. The data operations themselves look pretty straightforward; a serious workload of any magnitude is a "leave the server and make yourself a nice lunch" territory, at the very least.

    • chuckula
    • 3 years ago

    So AMD showed off how badass they are when you don’t put enough memory into the Intel system.

    Just wait until Intel shows an Atom destroying the 1800X when the 1800X doesn’t have a motherboard!

      • chuckula
      • 3 years ago

      For anybody who thinks I was trolling above, I wasn’t: AMD intentionally gimped the Intel system with a reduced amount of memory to show off how supposedly awesome Naples is.

      A 3 second trip to ARK would show you that the E5-2699A V4 used in that benchmark is officially rated to support 1.54 TB (that’s [b<]TERA[/b<]bytes) of RAM on a single socket: [url<]http://ark.intel.com/products/96899/Intel-Xeon-Processor-E5-2699A-v4-55M-Cache-2_40-GHz[/url<] So I'd like to see how fast Naples is when the Intel dual socket system is loaded with the > 3 TB of RAM that it actually supports and we up the data set size above a paltry 512GB of RAM. [Oh and one more thing: The Xeon also officially supports DDR4-2400, especially in a low-memory configuration like what AMD showed off. For some mysterious reason the model being displayed on stage only had 1866 running.... mysterious....]

        • anotherengineer
        • 3 years ago

        I would say you were trolling, because………….

        I think most people visiting TR are

        able to read
        knowledgeable about tech
        and can form their own conclusion after reading the details

        However, it seems you think different, judging by your posts, spelling out everything. Do you think the TR audience requires spoon feeding?

          • chuckula
          • 3 years ago

          [quote<]Do you think the TR audience requires spoon feeding?[/quote<] Tell ya what. I'll stop "spoon feeding" TR's audience when AMD has the cojones to just show off its own hardware by itself without gimmicky "bakeoff" comparisons that turn out to be dubious later on when the products actually launch. Even better: If Intel pulls a stunt like that against AMD, then I'll make sure I quote you against anybody who thinks that it's even remotely "unfair" or "deceptive" on Intel's part. Furthermore, considering I accurately called some of the issues that RyZen has had on the desktop with workloads that aren't trivially parallelizable [b<]MONTHS[/b<] ago due to its strong NUMA characteristics but that didn't stop a strong contingent of people around here from accusing TR of being in a huge anti-AMD conspiracy... then yes, I would say a large group of people around here need spoonfed in the worst kind of way.

            • derFunkenstein
            • 3 years ago

            It’s like that Cinebench dual-channel gimp all over again. If quad-channel memory didn’t make a difference on that benchmark, why give the air of suspicion? And if the extra 20 cores are enough to give Naples the edge in this benchmark (assuming the amount of memory limited the Xeon machine’s performance), why are they setting up the test incorrectly?

            • Rza79
            • 3 years ago

            TBH quad channel memory doesn’t matter for desktop usage.

            [url<]https://www.computerbase.de/2017-03/amd-ryzen-1800x-1700x-1700-test/4/#abschnitt_spielebenchmarks_im_detail[/url<] Scroll to halfway the page.

            • derFunkenstein
            • 3 years ago

            That’s my point. If it doesn’t matter, why did AMD gimp the Intel system? It makes them look guilty.

            • Rza79
            • 3 years ago

            My guess would be that they tried to keep everything around the two processors the same, including the memory. I don’t think they intended foul play. It was a stupid move though.

            • derFunkenstein
            • 3 years ago

            Agreed, they might not have intended to handicap anything in that case, though they could have gone with 4x4GB DIMMs and done just as well.

            Here, though, it looks intentional. As Count Chuckula rightly pointed out, the Intel CPUs support more memory than they’re being given. In this case the Intel server only has 24 DIMM slots where the Naples machine apparently had 32 of them, going by the third image in this post. That’s the only reason the Intel box failed to process the work load, and has nothing to do with memory support. The AMD rep clearly drew the conclusion that the Intel chip was maxed out on memory when that’s not the case.

            • anotherengineer
            • 3 years ago

            Nice rant.

            Don’t care about either company and/or their benchmarks, I can read.

            So basically Jeff should rename TR to chuckula’s spoon feeding site then?

            If you like spoon feeding, you should make an account over at WCCFtech 😉

            Fanboys are fanboys, don’t drop to their level and troll, because it’s just as annoying.
            Unless you’re going to be one of these trolls [url<]http://www.toonbarn.com/wordpress/wp-content/uploads/2016/07/Trolls_Snack_Pack.png[/url<] then that's ok 😉

            • raddude9
            • 3 years ago

            Chuckula “classic” is back!

            [quote<]If Intel pulls a stunt like that against AMD[/quote<] Intel haven't pulled any "stunts" against AMD recently because, frankly, they haven't needed to because they have been so far ahead. But are you honestly trying to say that when AMD was ahead in the past, Intel didn't pull some serious "stunts", like, illegal monopoly abuse stunts. Also, you totally ignored this last time I mentioned it, but when Intel try to break into new markets they are well capable of gimping competitors machines just to make their home-grown "benchmarks" look better: [url<]https://arstechnica.com/gadgets/2016/08/nvidia-intel-xeon-phi-deep-learning-gpu/[/url<] Can you get off your high horse now. This is the whole point of this web site you are spewing your pointless comments into. We can't take any company's word for how things really perform, so various entities perform tests (or reviews) in order to guide people. [quote<]Furthermore, considering I accurately called some of the issues that [/quote<] Really? Let me quote you again, from : [url<]https://techreport.com/forums/viewtopic.php?t=118444[/url<] [quote<]I'll tell you right now that this is going to produce strong NUMA behavior since there is going to be a noticeable penalty in moving data to the wrong core even inside of a single chip.[/quote<] Be honest, you were just trying to stir up a dose of FUD, because despite some very slight NUMA issues, Ryzen manages to beat many intel chips that are priced far higher.

            • slowriot
            • 3 years ago

            You do more to damage Intel’s reputation than anything else on TR. By MILES.

            • Klimax
            • 3 years ago

            Warning: Absence of logic. And thought.

            • rechicero
            • 2 years ago

            I guess Lisa Su doesnt have cojones, indeed.

          • srg86
          • 3 years ago

          I only skimmed the article and don’t normally watch the videos. So his post was actually helpful.

          imho The chip is *VERY* impressive, but the demonstration is shady, which doesn’t do them any favors. And yes if Intel did that there would be a crap storm……

          • Anovoca
          • 3 years ago

          The “TR audience” can indeed “form their own conclusions”, which is precisely why they don’t need you to call someone out for them. Next time you want to hate on someone leave the “TR audience” out of it.

          • cobalt
          • 3 years ago

          In my opinion, he made a good point which was not in writing in the article above. I didn’t watch the videos, I just read the text, and couldn’t figure out why the Intel system “couldn’t even load the working set”. The fact that they equipped it with less RAM is definitely worth emphasizing, because that’s not a comparison between CPUs anymore; I wouldn’t personally call that “spoon feeding” in this case.

          Now, the tone of his post was definitely on the sarcastic side, but that’s pretty normal.

            • raddude9
            • 3 years ago

            Umm, it is in writing in the 3rd image as plain as day, 512GB versus 384.

            Although, as I mentioned elsewhere it would be more clear if TR hadn’t cropped out the words “Demo Setup:” and “Both Systems AMD and INTEL have the following features”

            Other sites have the uncropped image for comparison:

            [url<]http://hothardware.com/reviews/amd-poised-to-disrupt-the-data-center-with-zen-based-naples-platform?page=2[/url<] I think Chuckula was just using the excuse for yet another bout of faux-outrage.

        • charged3800z24
        • 3 years ago

        Um…. seriously? The CPU supports 1.54 TB depending on the RAM type. The CPU can support up to 2400 MHZ RAM depending on the RAM type. The comparison is ECC registered dim support, not what rand crap can you put in the box.

        • Chrispy_
        • 3 years ago

        No, that was like-for-like using 16GB DIMMS.

        Sure you can put 64GB DIMMS in an Intel system but that is insanely expensive and only at reduced timings. Not only that, the intel platform shares each channel over three DIMMs whilst the AMD shares each channel over two DIMMs for reduced adressing contention.

        I don’t know what the maximum memory capacity of the Naples IMC is, but you can bet it’s not 16GB/DIMM. This test is just to prove the memory controller performance given the same DIMM.

        • the
        • 3 years ago

        AMD’s memory capacity was based around 16 GB DIMMs which is odd. 64 GB registered ECC DDR4 DIMMs are common place with 128 GB LR-DIMMs are around if you look hard enough. 256 GB LR-DIMMs have been announced, though I’m not sure of general availability.

        The thing is that [i<]both[/i<] AMD and Intel [i<]should[/i<] be able to use these high capacity DIMMs. AMD should retain a capacity advantage due to additional memory channels but at 4 TB/socket vs. 3 TB/socket, there are few workloads where that would be a critical difference. With regards to memory speed, if the Xeon E5 is operating with 3 DIMMs per channel, epsecially higher capacity LR DIMMs, memory speed does drop. The 2400 speeds are with a single DIMM per channel, with 2133 being the more common speed for most configurations still. Still, that is a bit of an unexpected performance hit on the Xeon.

        • ET3D
        • 3 years ago

        My guesses are:

        AMD used 16GB DIMMs. Why? Not sure. Because that’s what was easily available for the demo? Because that’s all AMD supports or larger DIMM’s are not yet certified? Anyway, AMD wanted to illustrate how 8 more RAM slots can help. Is this really a valid comparison? We’ll know once we get the specs for Naples.

        Why DDR4-1866 for the Intel? My guess is because that’s the maximum speed supported when 24 RAM slots are in use.

          • AnotherReader
          • 3 years ago

          Given that Bulldozer based Opterons supported 32GB LRDIMMs, it is extremely unlikely that Naples doesn’t support the latest LRDIMMs.

        • Gich
        • 3 years ago

        But is there a board that support that much memory?
        Real question cuz I do not know.

        • nutjob2
        • 3 years ago

        LOL, can you read? Can you think your way out of a wet paper bag?

        If you were to load up the Intel system with DIMMs large enough to have 3TB of memory, then you would be able to have even more memory for the AMD system. Unless you cheat and give Intel bigger DIMMs, then AMD can just handle more memory.

        You really do sound bitter about Intel’s overpriced dross being revealed for what it is.

        • freebird
        • 3 years ago

        The article states:

        “Finally, AMD increased the sample set size in its workload from one billion to four billion, at which point the Broadwell-E server couldn’t even load the working set.”

        So was the AMD system able to load the 4 Billion Sample set size and compute it? With the same amount of memory as the Intel system? Yeah, you can load a system up with more memory, but memory gets expensive buying 32 GB modules (usually needed to get to higher Memory limits) and they usually have to run slower also. I can’t comment much on the systems, since I’m at work and can’t view any YouTube videos to see what they were or how they were configured, but I assume they had the same OS & memory amounts.

        Besides, quit crying about marketing people that are PAID money to make their Product look the BEST they can in a comparison. EVERYONE does. I agree that is might be a best case scenario for Naples, but what company comes out and shows you a clip of their products WORSE case scenario…

        Maybe you should go try earning a living doing that Chuckula and tell us how you make out…

        • terranup16
        • 3 years ago

        Via LRDIMMs. If you’re Microsoft, Facebook, Google, or some other datacenter with a big, fat contact with Micron or another supplier for such DIMMs, not a big deal.

        But if you’re a smaller datacenter or you’re building for a specific project or something outside a datacenter, then just 32GB LRDIMMs start around $1k per as compared to 32GB RDIMMs coming in at a quarter of that cost.

        AMD also has a valid argument it can support its RAM capacity at a lower depth per channel, which is true since they’re offering up to 16 channels. That is important for feasibly being able to use those DIMMs effectively.

        They made some pretty vague claims about how Intel hasn’t been curating its server offerings to match actual needs and instead has pushed incremental fluff. When we hear from their engineers, I strongly suspect they’ll say that the theoretical 3TB of LRDIMMs you can put in an Intel system is a useless spec because of the losses incurred by DPC and other sacrifices made to achieve it and you’d be better off with multiple nodes at that point or adding GPGPU or some other compute enhancer which will bring its own additional RAM to the equation at that point and scale.

          • Waco
          • 3 years ago

          Current Dell pricing, no special discounts:

          64GB LRDIMM, 2400MT/s, Quad Rank, x4 Data Width [$1,353.57]
          128GB LRDIMM, 2400MT/s, Quad Rank, x4 Data Width [$7,067.75]

          You can outfit a Dell R930 with 12 TB of RAM. It’s a bit slower, but it’s nothing dramatic like you’re implying.

            • Krogoth
            • 3 years ago

            It can make a significant impact depending on the workload you are trying to do and cost difference alone makes it difficult to convince PHB-types to opt for the denser DIMMs in the system budget.

            That’s the angle that AMD was trying to pull here in the demonstration. Their newer platform offers more flexibility in memory capacities and budget then current Intel solutions. However, this will likely change with Intel’s new generation platform.

            • Waco
            • 3 years ago

            I’m fortunate enough to have no PHB-types in management that have any say in systems purchasing. 🙂

        • POLAR
        • 3 years ago

        From Intel ARK:
        Max # of Memory Channels: 4

      • ImSpartacus
      • 3 years ago

      Yeah, that seems a little sketchy.

      The guy said they equipped the systems as closely as possible in one video, but then admits that one system has noticeably more ram.

      Why is this fair? Maybe I’m missing something.

        • Anonymous Coward
        • 3 years ago

        +8 RAM slots?

      • willg
      • 3 years ago

      Maybe they were trying to demonstrate that by having more memory channels it’s possible to equip Naples with greater memory capacity by leveraging the sweet spot of DIMM price/density.

        • Chrispy_
        • 3 years ago

        At least somebody gets it!

      • CampinCarl
      • 3 years ago

      Is it perhaps down to cost, again? Could they be saying “look, with our system, you can afford to upgrade to 256×2 instead of 192×2”?

      I thought maybe it was an actual product-system limitation, but HP DL 380 Gen9’s will allow up to 3TB total for the new v4 processors. So I’m not sure why they decided to stop at 384 for the Xeon system.

      • WaltC
      • 3 years ago

      I doubt it would make much difference to the anti-AMD dunderheads…;) They’d just find another reason to pan the results. They sound like stuck records…;)

      • Unknown-Error
      • 3 years ago

      Gimping the Intel systems will only backfire on AMD. Fooling AMD fanbois is easy (even Homo-erectus would have had a higher intelligence) but actual professional enterprise crowd won’t fall for AMD trickery.

        • Anonymous Coward
        • 3 years ago

        Maybe they should have set up the Intel system with bigger DIMMs, which of course would also be slower. Nobody would have complained about that.

          • Waco
          • 3 years ago

          Exactly! Play on your strengths, but don’t create gamed tests that any purchaser will see through.

      • AnotherReader
      • 3 years ago

      It is sketchy. A better comparison would have been to load both to their maximum memory capacity. With 128 GB LRDIMMs, Naples should support 4TB.

      • slushpuppy007
      • 3 years ago

      cause the atom brick’ed its board.

      • wierdo
      • 3 years ago

      I thought they were just poking fun at the fact their platform supports more memory with the last test.

      To me it just said “with this much more memory we can even support things our competition simply cannot.” and that’s about it. No harm in that.

      • 223 Fan
      • 3 years ago

      To be fair AMD’s marketing department still thinks Ryzen is another iteration of the Bulldozer core and is marketing it the same way.

      • ET3D
      • 3 years ago

      Reading up the specs at Anandtech, Naples will support up to 4TB of RAM, so I think it’s clear that AMD intended to illustrate the difference in RAM size. Using 4TB vs. 3TB would likely have required a test that takes a lot longer to run, and would have cost a lot more.

      • Pancake
      • 3 years ago

      How about an atom-powered Xeon Phi? Huh? Huh? 1800X (or pretty much anything else) will be battered and bruised… I coulda been a contenda!

      • Krogoth
      • 3 years ago

      They were trying to showcase the difference between their memory subsystems by using a common DIMM size out in the field (16GiB DIMMs). Going for higher density increases the cost dramatically and also sacrifices memory performance (slower DIMMs).

      Don’t worry though. Intel’s next platform revamp in the multi-socket world will move itself to six-channel DDR4.

        • Waco
        • 3 years ago

        32 GB DIMMs seem to be the new hot-spot for best $/GB pricing, though. 🙂

      • NoOne ButMe
      • 3 years ago

      FYI, Naples will, at each DIMM Size class, have that much more memory…. 2TB v. 1.5, 1TB v. 768GB, 512GB v. 384GB.

      Bad testing. outside of x% of server market not like the test matters anyways. but still bad.

      Like when AMD did 390/390x testing where they made games use over 4GB of VRAM and compared to 980.

        • Waco
        • 3 years ago

        …on an E5 system, yes.

          • NoOne ButMe
          • 3 years ago

          I am under the impression Intel has no parts with 8 memory controllers or 16 DIMM slots per CPU currently.

          Currently it tops out at 4 channels with 3 DIMMS each.

          Skylake will bring 6 channels, don’t know if that will be 2-DIMMs, or 3-DIMMS each on the motherboards.

            • Waco
            • 3 years ago

            Right, but they have 4P systems, and those have 96 slots for four CPUs.

    • CampinCarl
    • 3 years ago

    Now, if they can just get either A) their own compiler + library suite that will rival ICC or B) work with the gnu folks to ensure gcc will compile it to be competitive, I might be able to convince someone to buy these.

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