AMD’s Naples datacenter CPUs will make an Epyc splash

We first heard about AMD's Zen-powered Naples datacenter CPUs back in March, and at its Financial Analyst Day today, AMD CEO Lisa Su revealed that these many-core CPUs will be called Epyc.

Su also showed off an Epyc package. This enormous hunk of silicon will offer up to 32 Zen cores, eight memory channels, and 128 PCI Express 3.0 lanes from each socket. You can read more about Epyc in our Naples reveal.

We expect to hear more about Epyc as the company's Financial Analyst Day progresses. Stay tuned for more news.

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    • EndlessWaves
    • 2 years ago

    Eh? PC

    • ronch
    • 2 years ago

    Gotta love all these facepalm AMD product names. Ryzen, Threadripper, and now Epyc.

    Good grief.

    • Bumper
    • 2 years ago

    I like the name. Reminds me of SPARC. Extreme parallel yield cpu

    • Tristan
    • 2 years ago

    single silicon for all CPU, from Ryzen 3 to Epyc with 32 cores
    Typical AMD

      • cygnus1
      • 2 years ago

      Intel does the same thing. You don’t think that all of the different models of quad core single memory channel CPU’s from Intel have different silicon do you? And the higher core count models with quad memory channel? For the high end Intel CPU’s (Core/Xeon) they have like 3 or maybe 4 total pieces of silicon that get cores/features selectively disabled to create their product differentiation. MCM’s are more efficient from a manufacturing perspective up front for new products. Give them time and they’ll integrate things and have some more specific silicon for different segments eventually.

    • alrey
    • 2 years ago

    maybe EPYC means epicenter — the cpu is the epicenter of an epic data center.

      • Mr Bill
      • 2 years ago

      Epipinephrine for the compute center!

    • Unknown-Error
    • 2 years ago

    Epyc Fayl?

    • maxxcool
    • 2 years ago

    AMD: How do we beat Intel in the server game ?
    Analysts: Can you fab big enough chips to bludgeon them to death with?
    AMD: YUP

    Seriously though, I hope the per thread performance is not impacted by all the required side channel jabber to keep things coherent.

    I’d love to buy this with some of my bonus cash ..

      • chuckula
      • 2 years ago

      Project M.O.A.R. is going to be EPYC!

      • the
      • 2 years ago

      Hopefully the Sea Micro acquisition will have paid off here.

      Though I would have expected more than a dual socket setup if that were the case. Then again, AMD hasn’t disclosed how their Infinity fabric can be bifurcated.

        • maxxcool
        • 2 years ago

        It will help for sure, i have some tepid excitement..

    • Chrispy_
    • 2 years ago

    Dat name tho.
    Srsly.

      • chuckula
      • 2 years ago

      The only problem is, four stories up they are talking about ThreadRipper and that makes Epyc seem like an amateur in the stupid name contest!

    • tsk
    • 2 years ago

    Why oh why couldn’t they stick with Opteron?

      • freebird
      • 2 years ago

      Or something cool like Itanium, right???

        • DreadCthulhu
        • 2 years ago

        To be fair, Itanium’s were pretty EPIC under the hood. 😉

      • Wirko
      • 2 years ago

      Yeah, “a pike” sound fishy.

      • ClickClick5
      • 2 years ago

      That cuts it. These names are just silly, but oh well.

      Xeon Gold?
      Eypc?

      :/

        • juzz86
        • 2 years ago

        Welcome to Marketing to the Next Generation 🙁

      • Ninjitsu
      • 2 years ago

      Opteron sounded too op3rat0r to them, so they went with something more 1337 and epyc instead.

      • shank15217
      • 2 years ago

      Because Opteron doesn’t have a very good reputation as a performance part since nearly a decade. Its good that they are retiring that line.

    • chuckula
    • 2 years ago

    Incidentally, Papermaster is on stage talking about how AMD is “defying” the slowing of Moore’s law.

    That’s fancy corporate talk for: Don’t expect 7nm products from GloFo before 2020.

      • Antimatter
      • 2 years ago

      They could move 7nm production to TSMC if they want to.

        • Thrashdog
        • 2 years ago

        I thought it’d been fairly well established at this point that TSMC’s process node designations were mostly marketing blather at this point?

    • derFunkenstein
    • 2 years ago

    Weird. It’s just four Ryzen chips duct-taped together until you get to PCIe connectivity. Then it’s 8x the lanes. I wonder if the consumer chips have 16 extra lanes that are partitioned off or if these are different dice? The former seems more likely, I think.

      • Waco
      • 2 years ago

      32 lanes per CCX pair jives for the most part with the consumer parts, no? 24 usable lanes + 8 lanes for chipset connectivity?

      Forgoing the chipset over PCIe (since much of it is on-chip) that makes 32 lanes available per CCX pair.

      EDIT: The name is predictably stupid, but no more stupid than the renaming Intel just dropped on the Xeon lines.

        • chuckula
        • 2 years ago

        128 lanes of PCI express is theoretically on the chip, but in a dual-socket system 64 of those lanes are dedicated to jabbering with the other socket.

        So it’s a theoretical choice of: 128 lanes of PCIe in a single-socket server or 128 lanes of PCIe in a dual socket server.

        There have been some actual prototypes of Naples motherboards where the actual usable PCI connectivity is in the range of about 112 lanes.

        [url<]https://www.servethehome.com/second-amd-naples-server-pictures-platform-block-diagram-112-pcie-lanes/[/url<]

          • Waco
          • 2 years ago

          Yep. I’m just glad they’re making the single-socket version expose *almost* all the lanes!

          It’s still far more (very much far more for 1P systems) versus 2P systems from Intel.

          • the
          • 2 years ago

          With 112 lanes, a motherboard can fill out all 7 slots in the ATX spec with 16 lane PCIe slots without the need for bridge chips. Fitting this large chip, 16 DIMM slots and 7 PCIe slots into an ATX board is another question.

        • psuedonymous
        • 2 years ago

        [quote<]x 32 lanes per CCX pair jives for the most part with the consumer parts, no? 24 usable lanes + 8 lanes for chipset connectivity?[/quote<]Desktop RyZen has 24 lanes: 16 to the GPU (or otherwise), 4x for NVME SSD (or otherwise) from the CPU, and 4x to the chipset (exposed directly on the X300/A300 non-chipset). 2 of those NVME lanes may be used for SATA ports, to bring the 2x ports from the CPU to 4x ports.

          • Waco
          • 2 years ago

          ?

          16x direct
          4x NVME / SATA
          4x chipset
          4x USB 3.1

          That leaves 4 unused, but I have to admit I haven’t kept up with the desktop parts as much. I would be *shocked* if there’s a different die under there.

        • derFunkenstein
        • 2 years ago

        Not sure how you arrived at the consumer chips giving the chipset 8 lanes.

        [url<]https://techreport.com/review/31366/amd-ryzen-7-1800x-ryzen-7-1700x-and-ryzen-7-1700-cpus-reviewed/2[/url<] From what I see, there are 16 PCIe 3.0 lanes available to the single or double x16 slots used for graphics, 4 more lanes available for M.2 x4 storage, and...that's it. Everything else is what's in the chipset. No discussion (at least in TR's review) about how the CPU talks to the chipset. But if that's really how it works, that's kind of deceptive. What good are lanes that are always tied up with chipset communication, and what good are lanes that are constantly tied up talking to other CPUs (as chuckula pointed out)?

          • Waco
          • 2 years ago

          4 more lanes for USB 3 connectivity, and the remainder I have to assume are chipset or unused.

          Using PCIe lanes versus a dedicated interconnect (for multiple sockets) is a great way to save costs and consolidate silicon. I can’t really fault AMD for that.

      • jts888
      • 2 years ago

      Ryzen has 2 blocks of 4+4+4+2+2 lane general purpose 12 Gbps PHYs that support ganging. The usual AM4 allocation is 16 for a x16 PCIe slot, 4 for a x4 slot, 4 for a NVMe/m.2 port, 4 for the chipset, and 4 (presumably the last pair of 2-lane PHYs) unadvertised.

      I’m assuming that AM4 exposes the last 4 lanes to the socket so the motherboard vendors can directly connect a select few IO controllers (namely 1GbE and extra USB), helping to reduce PCB traces running between the chipset and rear panel (and cutting across the PCIe AIB lines).

    • chuckula
    • 2 years ago

    OMG. They just set themselves up big time.

    Incidentally, I’m streaming the Financial Analysts day now.
    Not all that exciting, especially when Papermaster says stuff that Raj already said… except Raj was excited.

      • freebird
      • 2 years ago

      Yeah, AMD’s stock is up almost 12% today… and another 3% after hours…

        • chuckula
        • 2 years ago

        It’s re-entering hype mode after taking the biggest single-day dump in over a decade after they announced the Q1 loss.

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