Micron hits 16 Gbps with GDDR5X and talks about GDDR6

It got a bit buried in the Computex shuffle, but at the beginning of the month Micron posted a blog entry laying out in broad strokes the company's plans for graphics card memory. The big news in the piece is that the company has managed to get its GDDR5X memory running at 16 Gbps in a lab scenario. Micron also says it will have functional GDDR6 silicon "very soon."

Regarding the GDDR5X news, the company says that the extremely high speeds were achieved using "a meaningful sample size" of its mass-production GDDR5X memory. That means that these results aren't simulated or using exotic silicon. The observation was made inside a testing facility, though, so don't get too excited yet—it's not likely we'll be seeing GDDR5X at 16 Gbps on graphics cards anytime soon.

The post provides a few interesting details about GDDR6 and how it differs from GDDR5X. Notably, while GDDR5 is typically configured with 16- or 32-bit-wide I/O, GDDR6 will support two 8- or 16-bit-wide channels. Micron doesn't explain what the benefits of such a configuration are, but we can speculate that a reduced-power single-channel mode could be useful in mobile devices. GDDR6 also uses a larger package than its predecessor despite having ten fewer contacts. Micron notes that the distance between contacts is slightly greater as a result.

Unfortunately, we probably won't be seeing GDDR6 in actual products for a while. Micron's Kris Kido says that the company expects to have the new memory in production by "early 2018." That would imply that graphics cards with the new chips onboard aren't likely to show up until late next year at the earliest.

Looking back almost two years ago to the launch of the Radeon R9 Nano, it seemed like HBM might really shake things up. At this stage, that hasn't really been the case. The technology itself isn't at fault; the benefits are real. One would guess that the reasons why HBM isn't more widely-used are related to supply and pricing. High-speed GDDR memory may not have the power-consumption or space-saving benefits of HBM, but at least the performance is there. These are interesting times for the high-speed memory market, and we're very curious to see what lies ahead.

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    • the
    • 2 years ago

    [quote<] GDDR6 will support two 8- or 16-bit-wide channels. Micron doesn't explain what the benefits of such a configuration are, but we can speculate that a reduced-power single-channel mode could be useful in mobile devices.[/quote<] The main reason for splitting the bus is mainly due to skew. Instead of ensuring that all 32 bits of a bus arrive at the same time, only 8 or 16 need to be aligned which permits easier trace routing at higher clock speeds. The memory controller is responsible for aligning data transfers across multiple buses. Another potential benefit is that the entire chip might be addressable from a single link. The benefit here would be an increase in memory capacity by using two chips instead of a single one on a unified bus. Though there are could be some technical reasons I'm not privy too that may prevent this in the GDDR6 spec.

      • ImSpartacus
      • 2 years ago

      I just want to say that I appreciate the context.

      I’ve been interested in the difference between GDDR6 and GDDR5X ever since I heard their theoretical clock ranges were effectively on top of each other.

      The table in that blog is helpful, but you kinda go, “ok… so two channels are better than one…” without the necessary context.

      • willmore
      • 2 years ago

      More and smaller channels would have the skew benefits that you mention–which will lead to higher clock speeds.

      The other benefit is that there will be more channels for a given bus width. This means that efficiencies in the memory controller can leverage smaller transfers–which we’ll see more of with GPU compute.

      Those extra pins are for the additional control signals needed for the doubling of channels that’s happening. They’re halving the width of channels, but doubling the # of them. That keeps the # of data pins the same, but requires more control signals for that extra channel.

    • Chrispy_
    • 2 years ago

    HBM is still too low-volume to have come down in price.

    In theory the cost of HBM stacks shouldn’t be that much more than GDDR stacks, but it’s just that GDDR fits into existing high-volume designs for which all the economies of scale apply, whilst HBM is still fairly immature and requires process changes to implement.

    I would hope that HBM2 can be increased in capacity and speed at the same time that production can be ramped up enough to improve cost efficiency. Then it’ll simply be a case of using the right technology for the right situation; HBM for power-efficient, high-density situations and GDDR for large VRAM quantities at a the budget end of the spectrum.

    GDDR5X is an interesting anomaly since they expect it to scale up in performance without issues. I’ll believe that when I see it!

      • UberGerbil
      • 2 years ago

      Yeah, HBM is stuck in a rather unfortunate corner. Arguably the best place for it is APU designs in laptops, where it could function as both system and graphics memory and provide a real performance advantage compared to traditional IGPs without some of the complexity and cooling requirements of discrete GPU — and where the inability to add additional memory is at least tolerated. But it’s too expensive for that, coming in a prices where the conventional dGPU “gaming” laptops already live. At its current pricing it really needs to find a niche in enterprise, where a lot of exotic new techs hang out until they become commodities that can be enjoyed by the masses. But it doesn’t have any real advantages for that market, and the disadvantages are all too real.

        • guardianl
        • 2 years ago

        HBM shared memory wouldn’t make much sense in today’s APUs unfortunately.

        Example: PS4/XB1 have a shared memory APU design with a shared memory controller. However because of tons of technical reasons (like ordering) the usage of the memory controller is exclusive to one of the CPU/GPU at a time. And the CPU can only use 10-20% of the available bandwidth because memory accesses tend to be narrower (64 bit for the CPU vs 256+ bit for the GPU). So the CPU might use 50% “wall clock” time of the shared memory controller and that leaves the GPU with only 50% of the theoretical bandwidth.

        So for an APU with HBM a 1 GB HBM stack at 256 GB/s might give the onboard GPU 128 GB/s in practice. That’s nice, but at the interposer + HBM cost it’s probably cheaper to put in a discrete GPU + GDDR. So at best you might save a very modest amount of power at a huge expense.

          • ImSpartacus
          • 2 years ago

          That’s pretty terrible to hear, but it’s probably why we haven’t seen HBM in APU roadmaps (e.g. Raven Ridge, etc).

      • ImSpartacus
      • 2 years ago

      I agree – I was surprised to see Micron continue to invest in GDDR5X.

      It looks like they are aiming to take it all the way to their initial 16 Gbps projections.

      I can only assume that it shares quite a bit of overlap in R&D with GDDR6, which appears to have a more stable future.

    • psuedonymous
    • 2 years ago

    [quote<]The technology itself isn't at fault; the benefits are real. [/quote<]The theoretical benefits, or the benefits when you use reticule (and wallet) busting supermassive interposers to cram on more dies onto insane enterprise-budgets-only GPUs. But in terms of practical bandwidth for regular GPUs for consumers, HBM and HBM2 do not offer more than a 'conventional' layout of GDDRx chips, and in some cases (e.g. Vega's 2-die layout) offer less. Even in terms of size and power consumption, HBM has not been a winner so far. For example, the R9 Nano is infamous in ITX circles for having such an insanely bursty power draw that it's basically impossible to use with DC-DC PSUs and external AC-DC bricks (because it will trip the OCP with regularity), meaning that with super-tiny cases like the NFC S4 Mini, you can cram in a 1080 (and possible a 1080Ti if Josh makes a bezel with a little more clearance), but not an R9 Nano. HBM is great for the damn-the-cost bleeding edge of performance, but it needs some more time before it makes sense to filter it down to consumers. The cost is too high, and the benefits over GDDR just don't exist there.

      • DoomGuy64
      • 2 years ago

      HBM isn’t to blame for the Fury’s power consumption. That’s solely on the Fury chip itself, which is pretty inefficient in comparison to Nvidia’s chips using TBR. DX12 is the only saving grace of AMD’s chips, which still can’t surpass nvidia unless games are well optimized for it, and the 1080 will still outperform it in most cases.

      The only real positive thing about the Fury is that it actually is capable of playing dx11 games smoothly, unlike gcn 1.0 which was pretty terrible until after years of driver updates compensating for it’s hardware imbalances. The Fury will at least run games smoothly day one, unlike GCN 1.0 which rarely did, and driver features have also come close to matching parity with Nvidia. eg: ReLive.

      We probably won’t see the real benefit of HBM until Vega, because the Fury just wasn’t balanced enough to use it properly.

        • psuedonymous
        • 2 years ago

        [quote<]We probably won't see the real benefit of HBM until Vega, because the Fury just wasn't balanced enough to use it properly.[/quote<]Even on Vega's Frontier Edition, where bandwidth is going to be pushed as far as possible to satisfy the Machine Learning market, memory bandwidth is below the Fury, the latest Titan, and even the 1080Ti.

          • DoomGuy64
          • 2 years ago

          It’s still meaningless if the GPU can’t use it, and Vega should have better compression than Fury. Nvidia got away with not using HBM or high bus widths, so obviously there’s a cut off point for bandwidth needs. 64 ROPs are going to be a bigger bottleneck than Vega’s bandwidth capabilities.

          The Ti on the other hand is such a monster GPU that it does need the bandwidth, or it would starve the GPU. For the most part, I think engineers know what they’re doing when they pair memory with a GPU. The Fury was more of a concept GPU than a properly balanced piece of hardware. The ecosystem for dx12 was not there at time of launch, nor was hardware efficiency, so HBM was likely tacked on for experience with the technology and compensating for chip issues. Doesn’t hurt to have high paper numbers for marketing either.

          The real bandwidth problem is on crippled midrange hardware, which often make those cards unusable past 1080p. 256-bit is kind of a sweet spot for most GPUs, and anything higher requires a monster chip that can use it. Slightly slower HBM isn’t an issue, chip efficiency is, and higher memory sizes are also a requirement for higher detail levels. Vega is going to hit the memory sweet spot far better than the Fury, simply because it’s been better designed for it from past experience.

    • chuckula
    • 2 years ago

    Looks like plain ol’ GDDR is not going the way of the Dodo this decade.

    I’m still hopeful that stacked RAM will come down in price & improve in performance for regular customers, but it looks to be a gradual process at this point.

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