Toshiba prepares a 96-layer 3D NAND parfait

Toshiba's announcement of four-bit QLC NAND flash isn't the only big event in the realm of flash memory production today. The company has also let the world know that it's begun producing fourth-generation BiCS TLC 3D NAND silicon, developed in a joint venture with Western Digital. The new generation chips stack 96 layers in order to build 256 Gb (32 GB) packages.

The announcement of 96-layer production follows the last leap to 64 layers, a technology that started showing up in consumer products earlier this year. NAND endurance generally decreases with shrinking feature size, so increasing the number of layers represents a way to increase data density without shortening a drive's lifespan. According to Toshiba, the new layer arrangement works out to a 40% increase in storage density when compared to previous-generation 64-layer technology.

Toshiba also has plans to apply the 96-layer manufacturing process to producing larger 512 Gb (64 GB) 3D NAND chips and QLC silicon in the future. The 3D TLC chips described in this announcement are designed for use in consumer electronics devices like SSDs, smartphone storage, and memory cards. These new chips will be produced in Toshiba's facilities in Yokkaichi, Japan starting in 2018.

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    • hasseb64
    • 2 years ago

    New tech should mean lower prices but it seems that margins raise, they will not get my money for a while for sure

    • strangerguy
    • 2 years ago

    “How soon can we replace our already crappy TLCs drive with this QLC thing while charging same or higher prices?”

    -Totally not-greedy flash device execs.

    • JosiahBradley
    • 2 years ago

    Completely pointless as nand prices continue to suck. Trying to recommend 512GB drives to people at prices I was buying TB before.

    • just brew it!
    • 2 years ago

    QLC…? Ugh.

      • Kougar
      • 2 years ago

      Going by the 100-150 P/E rating, won’t have to remotely worry about consumer SSDs adopting those. Looks like they will be used for thumbdrives and niche SSDs built specifically for WORM applications.

        • just brew it!
        • 2 years ago

        .. and the thumbdrive race to the bottom continues.

      • willmore
      • 2 years ago

      They’re calling it ‘archival grade’ flash. We’re getting closer and closer to that Write Only Memory. (That’s a joke for engineers of a certain age)

        • just brew it!
        • 2 years ago

        WORM (Write Once Read Many) is also a thing. There’s a market for systems that can cheaply archive unchanging data for long periods of time.

        That said, I’d still be concerned about leakage with QLC in archival applications.

      • Laykun
      • 2 years ago

      I know right? PLC is where it’s at.

    • DPete27
    • 2 years ago

    What’s the height difference between a 96 layer 3D NAND chip and a planar one?

      • chuckula
      • 2 years ago

      Zero assuming they are both formed from a standard silicon wafer (and they generally are).

      The layers are etched down into the wafer and probably only occupy a very small fraction of the physical thickness of the wafer. This isn’t an instance of stacking the chips on top of each other to form the 96 layer chip.

        • just brew it!
        • 2 years ago

        That’s not entirely correct. They deposit additional layers of materials onto the wafer via CVD, then etch into [i<]those[/i<] to form the vertical stacks of memory cells. So it is slightly thicker, but only microscopically so. There's also research going on to do actual die stacking, as we're approaching the limit for the current 3D tech.

          • Kougar
          • 2 years ago

          Anandtech believes this 96-layer part is actually using that die stacking (string stacking) tech already.

            • just brew it!
            • 2 years ago

            Oh. Interesting.

            Makes sense though, we’ve already had stacked dies for SOCs for a few years, IIRC.

    • tacitust
    • 2 years ago

    Is there a known limit on the number of layers that can be stacked on top of each other? I’m assuming the law of diminishing returns kicks in at some point, but how far can they go before it does?

      • Kougar
      • 2 years ago

      I had read (probably a past Anandtech piece) that 64-72 was the expected cap. What’s interesting is something called “NAND string stacking” is supposed to bypass this problem, and it appears WD has implemented this to bypass the stack limit.

      Some info here [url<]https://www.theregister.co.uk/2016/07/06/the_stretch_of_the_3d_etch/[/url<]

    • chuckula
    • 2 years ago

    [url=https://www.youtube.com/watch?v=W-D8Qq2huHw<]Everybody loves parfaits.[/url<]

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