Intel Xeon W CPUs take Skylake Server to workstations

Intel's Skylake-X CPUs put some of the best elements of the company's Xeon CPUs on the enthusiast desktop, but those chips miss out on a couple of features that many would consider mandatory for workstation-class builds. The lack of ECC RAM support from the X299 platform is the most pressing omission, but businesses might also want support for Intel's vPro suite of remote management tools. Some others might also want AVX-512 support with dual AVX-512 FMA units in lower-core-count chips, a feature that's hobbled on lower-end Skylake-X CPUs and missing entirely from Kaby Lake-X chips. Yet another class of user might want more PCIe 3.0 connectivity from the CPU than lower-end Skylake-X CPUs provide. 

  Base

clock

speed

(GHz)

Turbo

Boost

2.0 speed

(GHz)

Cores/

threads

AVX-512

FMAs/core

L3

cache

(MB)

PCIe

3.0

lanes

Memory

support

TDP Socket Price
W-2195 2.3 4.3 18/36 2 24.75 48 Four channels

DDR4-2666 with ECC

140W LGA 2066 TBA
W-2175 TBA TBA 14/28 19.25 TBA
W-2155 3.3 4.5 10/20 13.75 $1440
W-2145 3.7 4.5 8/16 11 $1113
W-2135 3.7 4.5 6/12 8.25 $835
W-2133 3.6 3.9 6/12 8.25 $617
W-2125 4.0 4.5 4/8 8.25 120W $444
W-2123 3.6 3.9 4/8 8.25 $294

Intel's new Xeon W family of CPUs should satisfy all of those users with a refreshingly consistent feature set. (Sorry, Skylake-X builders.) These single-socket workstation chips range from four cores and eight threads to 18 cores and 36 threads, and they're all built using fully-enabled Skylake Server cores. That means every chip gets four channels of DDR4-2666 RAM with ECC support, two AVX-512 FMA units per core, and 48 lanes of PCIe 3.0 from the CPU. Four of those lanes likely power the DMI 3.0 connection to the chipset, so final systems will likely have the same 44 lanes for I/O and peripherals as other Skylake Server parts. The only thing one seems to lose in the move to W-town is support for Intel's Turbo Boost Max 3.0 feature.

The entry-level Skylake-W parts are the most interesting of the bunch because they underscore the "scalable" in Xeon Scalable Processor. The Xeon W-2123 and W-2125 both offer four cores and eight threads, but they boast 8.25 MB of L3 cache—much more than the "natural" 1.375 MB of L3 per core from the Skylake Server microarchitecture. Those resource provisions suggest that Intel is able to selectively disable cores on its on-die mesh without disabling their associated L3 caches. These chips have 120W TDPs, and their only major difference is in clock speed: 3.6 GHz base and 3.9 GHz Turbo speeds for the W-2123, and 4.0 GHz base and 4.5 GHz Turbo for the W-2125.

Moving up the Xeon W product stack reveals more familiar faces. Intel will offer two six-core, 12-thread parts that differ only in clock speeds; a single eight-core, 16-thread part, a 10-core, 20-thread chip, a 14-core, 28-thread part, and an 18-core, 36-thread beast at the top of the stack. 12-core and 16-core members of the family are absent for now, but it's not a stretch to imagine they could show up down the line.

In another workstation-friendly touch, all Xeon W CPUs also offer support for up to 512GB of memory, as opposed to 128GB for Skylake-X parts. As we already noted, ECC RAM support is included in these CPUs, compared to the hard no-go one gets with Skylake-X.

While each Xeon W CPU uses the LGA 2066 socket that we know from the X299 desktop platform, these chips will require a new chipset and new motherboards to function. The C422 chipset is broadly similar to X299. It offers 24 lanes of PCIe 3.0, as many as 10 USB 3.0 ports, as many as eight SATA 6Gbps ports, and integrated Gigabit Ethernet. How those PCIe lanes, USB ports, and SATA ports are balanced in shipping products will depend on manufacturer implementations. Unlike X299, however, C422 includes support for Intel's vPro remote management suite and Rapid Storage Technology Enterprise 5.0 features.

The C422 chipset also includes an apparently new tier of Intel's Reliability, Serviceability, and Availability (RAS) features called Standard Workstation. We're seeking more information on what these features might include, but the Standard tier for Skylake Xeons includes Advanced Error Detection and Correction monitoring within CPU cores' integer units, as well as Single DRAM Device Corrections, or SDDC. Xeon W chips may also support PCI Express End-to-End CRC Checking for data integrity on those buses. Although it's in the Standard RAS tier for server CPUs, we doubt Xeon Ws support Ultra Path Interconnect Protocol Protection, if only because these chips don't use UPI.

Intel didn't annouce a release date for Xeon W CPUs, but given the availability of Skylake-X chips in the market already and the fact that Xeon W-compatible motherboards are already rolling out, we'd expect these chips to be widely available soon.

Comments closed
    • lycium
    • 2 years ago

    Intel are forever touting their dual AVX units, but the CPU clocks down when AVX instructions are detected, which can make the overall instruction mix slower in some cases.

    I don’t know if AMD are clocking down on AVX instructions, but one way or another they’re doing just fine without the dual AVX units.

      • NoOne ButMe
      • 2 years ago

      For code written to utilize the AVX units to their potential, it is faster, despite the slowdown.

      How AVX heavy your code needs to be for it to be positive, hm. Good question. I’m sure someone has answered it. If not, interested to find out myself.

        • the
        • 2 years ago

        At a high level, figuring this out would be a specialized version of [url=https://en.wikipedia.org/wiki/Amdahl%27s_law<]Amdahl's Law[/url<] to account of the frequency changes between serial and parallel portions: making the parallel code faster also makes the serial code slower. Thus for code with AVX sprinkled in a few spots, there may not be any sort of overall speed gain conceptually. There are a couple of other factors in implementation that are more difficult to add to the higher level work too. There are three additional factors: AVX clock down time, non-AVX clock up time, AVX width wake up time, AVX width reduction time. AVX clock down time is pretty straight forward: it is the time it to reduce the clock speed down and increase voltage to AVX units as appropriate. non-AVX clock uptime is the reverse which impacts serial performance when the AVX code had just completed executing but the serial section continues on. [url=http://www.agner.org/optimize/blog/read.php?i=415<]AVX width wake up time[/url<] is the time it takes to enable full width AVX execution when previously using only narrow instructions. As a power saving technique, Intel will gate the upper half of a 256 bit AVX unit while performing 128 bit operations. Thus going from AVX 128 bit to 256 bit instructions has a bit of delay before full throughput is happening. Presumably the new Sky Lake EP chips have another width wakeup time to go from 256 bit wide to 512 bit wide but I have not yet seen this confirmed. Width wake up time can take place concurrently with AVX clock down time. There is also a width reduction time before the upper AVX bits go into a power saving state. This width reduction time has no direct impact on performance as it happens only when the upper bits are idle. The main impact is power consumption. As fine grained as power consumption is, keeping cores in a higher power state may prevent other cores from entering higher turbo states, thus indirectly impacting performance.

    • ronch
    • 2 years ago

    While the top models of this lineup will probably edge out Threadripper the thing is, Threadripper can be a better choice if you’re basing your buying decision on the price points at which Threadripper is available. The 1950X, for example, is a bit cheaper than the W2145 but gives you 16 cores vs 8. Per core, Intel will likely win, but it’s not like Threadrippers are poor single thread performers and buyers in this class of chips know these things are meant for high thread counts. It’s the same with the 1920X vs the W2135: twice the cores.

    I must say Threadripper is looking good here. If your apps like having tons of threads I think Threadripper is a very solid choice unless (and I’m no expert on this) licensing fees per core are an issue.

    • ronch
    • 2 years ago

    So, is Ryzen in trouble?

      • srg86
      • 2 years ago

      I can’t imagine why it would be.

        • ronch
        • 2 years ago

        So, is Ryzen (Threadripper) not in trouble?

          • tipoo
          • 2 years ago

          10 Intel cores are still 440 dollars more expensive than 16 AMD ones. They’ll be better per core but not enough for the core+cost gulf.

          I also think anyone looking at dual AVX-512 FMAs knows what they want…So I think both can and will exist with not much bleedover.

            • ronch
            • 2 years ago

            Yup, after looking at the numbers I think Threadripper has something going for it here.

            (Well that’s me. I shoot before I look. I comment before I read! ^_^ )

            • the
            • 2 years ago

            The more important factor is that Intel isn’t nerfing IO on the Xeon Ws. That is the weak spot of consumer socket 2066 chips vs. Threadripper. While Threadripper does have more PCIe lanes, than socket 2066 Xeons, there is no dire shortage on the low end.

            Dual FMA AVX-512 units also implies that these Xeons can be more competitive at lower core counts. Threadripper has an edge cover consumer socket 2066 chips due to artificial product segmentation by Intel. This is a self inflicted wound here.

            Ultimately these Xeons are what Intel should have been offering on socket 2066 for consumers from the start.

            • Krogoth
            • 2 years ago

            Exactly.

            Ryzen and Threadripper put a nice fire under Intel. They are taking the kiddie gloves off and are dropping artificial segmentation crap.

    • AMDisDEC
    • 2 years ago

    Need NSA’s High Assurance Platform (HAP) enable software to disable the Intel M.E. before I’d use any Intel product.

      • srg86
      • 2 years ago

      Since AMD has the same thing in PSP, what are you going to use? RISC-V?…

        • AMDisDEC
        • 2 years ago

        LOL. AMD doesn’t have the same thing, and AMD CPUs aren’t made where Intel’s are either.

          • chuckula
          • 2 years ago

          [quote<]LOL. AMD doesn't have the same thing, [/quote<] You know, for somebody who clearly has a religious adherence to AMD you might want to educate yourself about AMD's product line: [url<]https://www.amd.com/Documents/out-of-band-client-management-overview.pdf[/url<] [quote<]AMD CPUs aren't made where Intel's are either.[/quote<] That's like saying that because cyanide isn't manufactured at a rat poison factory that it's totally healthy for you.

            • AMDisDEC
            • 2 years ago

            Not apples to apples comparison.
            LOL! Who holds the IP for cyanide, and how do you differentiate it in the market? j/k

            You’re making it sound as if an Management CPU is an off-the-shelf commodity that AMD and Intel purchase off-the-shelf and install. By your logic, there is no difference between the internal fabrics either.

            Company history are at play here.
            Intel has a long and deep history with the DoD and NSA, while AMD does not.
            The DoD forced Intel to make AMD a second source, but AMD never really chased the military business like Intel did.
            If I were to chose which company were more likely to have a contract with the NSA to provide backdoor access, it would be Intel.
            Plus, geography is significant. Intel – Israel is much more likely to design in trap doors.
            I’m not sure exactly where the Zen design team is but I’m sure it isn’t Israel.

            This post should be worth at least -20 downvotes so, don’t let me down.

    • Krogoth
    • 2 years ago

    Nevermind, it looks like W-2125 are actually binned Skylake-X chips geared for clockspeed over core count. Not an abortion like Kaby-Lake-X chips.

    They make tending offers over Coffee Lake assuming you don’t need or care for overclocking.

      • chuckula
      • 2 years ago

      When you copy-n-pasted that post from the five other articles where you made the exact same comment referring to the HEDT platform you should have done a little more than just add the model numbers of the new chips to the front of your recycled material.

      If you had bothered to read the article you’d notice that the 2123 & 2125 Xeons have literally nothing to do with Kaby Lake X whatsoever.

      Your first hint would have been the support for Quad-Channel ECC RAM.

      Your second hint would have been the cache architecture that literally can’t be in a Kaby Lake part.

    • juzz86
    • 2 years ago

    So the 2125 boosts to the same limits as the 7740X, and has 48 PCIE lanes? That’s an… interesting move.

    I wonder if there’ll be a market for ‘gaming’ C422 boards, like for C232.

      • Krogoth
      • 2 years ago

      I wouldn’t be surprised that some vendors decided to go that route as competitive solution to the Threadripper family.

        • juzz86
        • 2 years ago

        Definitely. Colour me very surprised by Intel’s aggressive turbo clocks this time around – they’ve broken precedent this generation.

        I know which way I’d be going if these plugged into X299, that’s for sure.

    • blastdoor
    • 2 years ago

    I guess this is what will be going in the iMac Pro.

      • chuckula
      • 2 years ago

      He said with Eeyore’s voice and a sigh.

        • blastdoor
        • 2 years ago

        Pretty much 🙂

          • chuckula
          • 2 years ago

          Why does Apple cripple us with pathetic 18 core multi-teraflop Skylakes when we could get similar geekbench scores with an A11?!?!??!!??!?!

          WHY APPLE WHY!!!

            • blastdoor
            • 2 years ago

            Har har har.

            My complaint isn’t the Xeon performance, it’s the Xeon price.

            Threadripper is a far better price/performance proposition but I suspect Apple views Threadripper as an untested product and AMD as a highly unreliable supplier (for CPUs)…. and that view isn’t exactly wrong.

            The annoying thing, though, is that Apple has had the resources to change this reality for many years but has chosen not to try. Apple could have invested in AMD (if not directly, then through product pre-purchases or whatever accounting mechanism made everyone happy) years ago to create a better alternative to Intel. And I’m sure AMD would have gladly made the fruits of such investment exclusive to Apple — AMD would gladly do anything for a cash lifeline.

            Alternatively, Apple could have developed their own ARM-based CPUs for Macs. That would not have meant dropping an A11 into a Mac Pro (chuckula loves a good straw man). But what Apple has achieved with their iPhone SOCs demonstrates that the notion that only Intel has been blessed by the gods with the ability to make great CPU designs is just clearly wrong. Apple has had the talent, the money, and the time to make a great ARM-based CPU for the Mac — they just chose not to do so.

            • tipoo
            • 2 years ago

            My instinct is that they havn’t chosen not to do so, just not to do so YET. They want to make sure that if they make an Apple-like transition, they won’t be embarassed the next year if Intel makes a better design, so they want to make sure they can make better chips top to bottom through their portfolio. Lagging PowerPC performance in its latter years must be a sore memory.

            They’re a crouching cat with the “SOON” look on their face. I wanna see it. The iPhone in my pocket is as good per clock as Skylake Core M ultrabooks, and probably better per watt, I want to see how far this architecture can scale with more power and active cooling, more power for bandwidth IO, more cores…

            A10X in a clamshell would already be an upgrade over the base Core M Macbooks.

            • blastdoor
            • 2 years ago

            I don’t think they’re a crouching cat… I think they are a cat with a startled look on its face after jumping up to catch a bird and running smack into a glass ceiling.

            Back around 2012 Apple vastly overestimated what iPad sales would do relative to the Mac. They pounced hard on the iPad and ran into that glass ceiling.

            I actually don’t blame them going aggressively after the iPad. I do think the iPad had, and still has, a lot of potential. If anything, they should have been more aggressive on the iPad (particularly on the software and services side; particularly in education). But I do blame them for neglecting the Mac.

            The positive side is that I think they now appreciate that neglecting the Mac was a big mistake, and they do appear to be focusing on it again. Maybe that renewed focus will lead them to now make investments in CPU design that they should have (and could have) made 5 years ago. But even if they do make such investments now, we won’t see the fruits of it for a while yet.

            • NTMBK
            • 2 years ago

            The iPad is still a $5bn/quarter business, which mostly reuses R&D from the iPhone. It’s “only” an eighth of the size of the iPhone business, but it’s still almost the same size as the entire Mac business. I don’t think that anyone at Apple should be unhappy about creating a business that size.

            Developing a custom CPU for the extremely niche ultra-high-end desktop market seems like a poor use of Apple’s money, unless they reuse the chip for e.g. their internal servers.

            • blastdoor
            • 2 years ago

            [quote<]Developing a custom CPU for the extremely niche ultra-high-end desktop market seems like a poor use of Apple's money[/quote<] The critical question is -- "compared to what?" What other investment could Apple be making that would have a better return? If one exists, it's not just that I don't see it -- Apple doesn't see it either. If they did, they wouldn't be spending tens of billions a year on stock buybacks and dividends. Also, the investment wouldn't apply just to the iMac Pro or Mac Pro, it would apply to the whole Mac lineup and, as you point out, potentially their internal servers. Put that altogether and it's pretty big. Look at what tiny little AMD has managed to do with Ryzen. Apple can and should do better.

            • NTMBK
            • 2 years ago

            Compared to sinking extra effort into improving their mobile CPU even further, for a starter 🙂 Talented CPU designers are a limited resource. Apple would need to spin up yet another world-beating CPU design team (or ideally two teams, so that they can alternate years). And this is liable to divert talent that would have gone into the mobile CPU teams, and dilute their excellence.

            To be honest I can absolutely believe that the mainstream Macbook market can be satisfied by the same CPU as the iPad Pro. But I think that if they want a high performance ARM CPU for workstations, they’d be better off buying one from Qualcomm or AMD.

            • tipoo
            • 2 years ago

            These areas have substantial overlap though. Kaby Lake scales from Core M to high end servers with the same core architecture. A10 is just as wide as Kaby Lake, and does as well per clock. Not sure about pipeline length (gosh, I wish we had that Anandtech deep dive that went missing), but point being they can already likely start to scale.

            They’re around (mobile) i3 performance with three fanless cores, if they went to six imagine how far they’d already be. And they seem to be the one per-core performance train that hasn’t slowed down so far (AMD made a leap, but may enter Intels slow-gains portion).

            • blastdoor
            • 2 years ago

            I totally agree.

            Everyone from MediaTek to AMD can slap together a bunch of cores. The trick is to design a core that’s worth something to begin with. Apple has already done that heavy lift.

            • blastdoor
            • 2 years ago

            [quote<]Talented CPU designers are a limited resource.[/quote<] And yet tiny, beleaguered AMD has managed to scrape together enough of these precious jewels to develop a perfectly cromulent CPU. People talk about Apple as if it's 1999. Folks, Apple has the resources!

            • the
            • 2 years ago

            The comparison should be made against continued use of x86 chips in this segment or utilizing external ARM core designs (ie from ARM themselves).

            The first is straight forward in terms of hardware cost: you know how much Intel will sell you chips for the volumes you move vs. the cost of developing your own chip plus how much it costs to make them from Samsung/TSMC. Depending on what Apple wants in terms of hardware, this could be lower today.

            The second is also straight forward for calculation. You have the same volume times chip price from Intel vs. similar volume * core count from ARM plus the manufacturing costs from Samsung/TSMC. Apple would have to be content with the alternative core designs as well as IO options available from 3rd party IP (USB, Ethernet etc.). The IP is there for a rapidly developed ARM desktop part if they wanted to go in this direction. I would also fathom that this is already cheaper than Intel due how this 3rd party IP can appear in chips several orders of magnitude less expensive than what Intel charges for CPUs.

            Regardless what the hardware comparison is, there will also be a relatively fixed cost to the priced of transitioning macOS to a new platform. The big variable here is if Apple would perform a clean break or if they would opt to support two hardware platforms simultaneously. While this would be a one time expense, it is likely larger than the savings Apple would have in terms of cost savings. The cost of this would be added onto either option above.

            • tipoo
            • 2 years ago

            The Mac business did show incredible staying power though, while the iPad had been waning until the 329 ‘budget’ model. Meanwhile Mac ASPs went up. A Mac is critical to a lot of people even if the selling price increases, the iPad, not as many cases where it is. I suspect (can I say Know?) that the Mac has a lot more loyalty while the iPad is just a nice to have.

            The clamshell form factor is just too perfect a one for productivity. So the A10X embarasses the Core M Macbook a bit…But so what. It’s still less comfortable to type on, more oragami to get a keyboard and screen in front of you, no cursor for fine text/editing selection…

            A10X and A11X in a Macbook like form factor…Now we’d be talking.

            • the
            • 2 years ago

            Apple knows how to do a platform transition, as they’ve done one about every ~10 years or so since the first Mac. So in that respect, we’re over due. 🙂

            The catch with every platform change is the issue of migrating the software. The nice thing here is that Apple has the walled garden of iOS which recently went through a 32 bit to 64 bit transition with little disruption. Apple is attempting to morph macOS into a walled garden as well but legacy remains an issue. Thus now they would have an easier time than before but still a headache.

            The other factor is that every platform transition Apple has done has been a clean break. Most of the discussion ‘why doesn’t Apple release an ARM laptop?’ has been in the context of just the MacBook or MacBook Air. They certainly good but that’d leave out the rest of the Mac platform (iMac, Mac Mini, Mac Pro etc.). Apple has never attempted to actively support two platforms simultaneously which is a far more difficult proposition than migration. Binaries would have to be made available for both platforms going forward as well as emulation software developed to support legacy x86 applications that wouldn’t get an ARM recompile. As long as Apple would offer x86 alongside ARM hardware, there would be the expectation that things would ‘just work’.

            If Apple were to migrate to just ARM, they would also have to introduce some high end SoC to compete with Intel Xeons. Issues like memory bandwidth can be scaled up by introducing additional memory controllers etc. Those are relatively straight forward to do. The more difficult prospect is increasing core counts for Apple’s proprietary designs. Little is known about how Apple’s CPUs communicate with each other on-die. I think it is safe to say they could scale up to a quad core (or 4+4 now that they’re doing their own big.LITTLE style implementation) but beyond that is completely known. If they’re using a ring bus, they’ll run into the same issues Intel did with their on-die bus. A cross bar would be good in terms of scaling but they consume power and are complex to design as node count increases. A grid/mesh-like topology used in recent Xeons sit between those two in hardware complexity but care has to be taken with regards to coherency (more than one path between nodes). As odd as it would be, Apple simply be using a shared bus in their iOS devices as that has some characteristics that work well in mobile but would [i<]effectively[/i<] prohibit beyond cores due to extremely poor scaling. Also I would dispute lagging PowerPC performance. The G5 class chips were nice, just that IBM couldn't get power consumption down to levels that could be placed into a laptop. That's most of Apple's unit sales which were stuck with G4 class chips. Apple could have gone with other faster G4 class chips from Freescale but that would have required them to develop a new chipset which Apple wasn't adapt at doing (see the first G5 chipset).

            • NTMBK
            • 2 years ago

            Don’t forget that Qualcomm have server-grade ARM SoCs launching this year. Just because Apple goes ARM doesn’t mean that they need to produce [i<]all[/i<] of the chips themselves.

            • the
            • 2 years ago

            Correct. They don’t even have to use entire chips. Utilizing ARM designed CPU cores to rapidly create a desktop style chip is also a viable option. This does mean that Apple would have to be content with what is offered by third parties to build a platform around.

            • tipoo
            • 2 years ago

            iirc those still aren’t as wide as Apples consumer chips, though performance will have to be seen. 4 wide vs 6 wide I think?

            • NTMBK
            • 2 years ago

            Qualcomm’s Falkor core is 8 wide.

            • tipoo
            • 2 years ago

            You’re looking at dispatch or execution ports, it’s indeed 4 wide decode at the front end, A10 is 6 wide. Issue width without context as I admittedly presented it generally refers to decode on the front end, Issue-width is the maximum number of instructions that can commence execution during the same cycle.

            The issue-width bounds the IPC that is possible.

            [url<]http://www.anandtech.com/show/11737/analyzing-falkors-microarchitecture-a-deep-dive-into-qualcomms-centriq-2400-for-windows-server-and-linux/5[/url<] [url<]http://www.anandtech.com/show/7910/apples-cyclone-microarchitecture-detailed[/url<] Apple was already at 6 with Cyclone in 2014.

            • blastdoor
            • 2 years ago

            Helpful link.

            I will be surprised (though pleasantly so) if Qualcomm manages to build a core that is remotely competitive with Intel’s Core.

            I will be unsurprised if Qualcomm’s comparative advantage here is throwing a bunch of little cores onto a die, running them at a low clock speed, and declaring a price/performance/watt victory on heavily threaded server workloads.

            In other words… I’m guessing what Qualcomm is offering here will not be appropriate for high end desktop / workstation applications, due to poor single thread performance. But hey — prove me wrong, Qualcomm! Competition is a great thing.

            • tipoo
            • 2 years ago

            Boy is it ever ironic that the company with probably the most suitable ARM cores for this space, probably has no interest in making server CPUs, eh, lol

            • NoOne ButMe
            • 2 years ago

            no interest in selling server CPUs.

            I have no doubt Apple will eventually at least trial run using their own Server chips. If they haven’t already.
            Recall, Apple had OSX running on x86 for years before they switched to Core.

            The real question becomes how many x86 CPUs for servers does Apple buy… the costs of designing, getting masks, et cetera, for themselves might be to high. 🙁

            • NTMBK
            • 2 years ago

            Ah, that makes a lot more sense. Thanks.

            • blastdoor
            • 2 years ago

            Everything involving computers in general and CPUs in particular is “hard” in the sense that you need a team of people with advanced degrees in order to pull it off.

            So in that sense, sure — adding more cores is “hard.” But compared to designing a worthwhile core in the first place? Color me skeptical.

            I just look at ThreadRipper and think — yeah, Apple can probably at least do that.

      • tipoo
      • 2 years ago

      *waits for someone to claim they can build an iMac Pro with this for half the price*

      😛

    • siberx
    • 2 years ago

    Any chance these chips will work in at least some X299 boards like has been possible with some previous HEDT platforms from Intel paired with Xeons (like, for example, the Xeon X5670 I have running in my X58)? The pricing for the low-end chips shown here is pretty reasonable if you have an application that needs lots of PCI-e lanes or memory channels but doesn’t also need a ton of cores.

      • blahsaysblah
      • 2 years ago

      No, they stopped that starting with Skylake. No xeons on Z/H, only Cxxx chipsets for Xeons.

        • smilingcrow
        • 2 years ago

        You seem to be talking about mainstream chipsets (Z/H) not the HEDT chipsets (X) so prior to this platform the X99 HEDT platform also supported Xeons whereas the mainstream chipset had already lost compatibility.
        It seems as if they are doing the same here but there is some confusion.

          • blahsaysblah
          • 2 years ago

          Z97/X99 supported Xeons.
          Starting with Z1xx, the low end Xeons moved to separate C2xx chipset.

          Considering X299 does not support ECC, it was clear, the C2xx was not a fluke. The C4xx seems to be match for X299.

          edit: that is, Intel wants a special SKU for you to allow price differentiation for themselves and partners. How else would Dell and HP charge even more for a Workstation,…

            • smilingcrow
            • 2 years ago

            I’m aware of the mainstream platform differentiation but this is a different conversation as the Xeons on X99 extended the platform significantly whereas on mainstream sockets not nearly so much.

            Maybe in theory Intel could allow these on X299 without ECC support assuming the CPUs don’t actually require it!
            In one sense it would extend the HEDT platform which could be seen as good but it would all then get rather messy and confusing even by Intel’s standard.
            It would mean X299 supported 3 ranges of CPUs! How unlike Intel that would be but with AMD breathing fire they may succumb to the heat.

            • spiketheaardvark
            • 2 years ago

            For the single socket processors, Is there anything else differentiating these things from the HEDT processor besides ECC support?

            • Krogoth
            • 2 years ago

            vPro support is a major one.

            • the
            • 2 years ago

            The extra 4 PCIe lanes offered by these Xeons may wind up going no where since they’re not part of the consumer Core i9s. Probably limited to 44 lanes if these Xeons were put into X299 boards. For the GPU crowd, that’d be the difference between 16x/16x/16x setup and a 16x/16x/8x setup.

    • chuckula
    • 2 years ago

    There’s a continuing set of inaccurate information floating around that only some Skylake X parts support AVX-512 or have “real” support for it.

    That hasn’t been supported by people testing the chips in real-world situations in which all of the Skylake X parts show pretty much what you would expect for AVX-512 support from the lowest-end 7800X up to the 7900X and beyond. Obviously the 7900X with more cores will beat a 7820X or 7800X, but the lower core-count parts do not show any per-core deficits in AVX-512.

    Y-cruncher has quite a bit of empirical information: [url<]http://www.numberworld.org/y-cruncher/[/url<] [quote<] It has been confirmed with benchmarks that all the Skylake X desktops have full-throughput FMA. This directly contradicts Intel's pre-release information. Subsequently, all the pre-release reviewers apparently got their information from the same inaccurate source from Intel. So if you are looking to purchase a Skylake X system for the purpose of AVX512, you do not need to spend $1000 to get the Core i9 7900X for the full AVX512. Either of the 6 or 8 core models (7800X and 7820X) will do.[/quote<] Edit: If you want to see how a wide range of chips compare in a heavy-duty 5 billion digit Y-cruncher run including results for the 7900X, Epyc 7601, Threaderipper 1950X, and Xeon Gold, you can check out this page: [url<]http://www.numberworld.org/y-cruncher/benchmarks/charts/5b.html[/url<]

      • Jeff Kampman
      • 2 years ago

      If this information is inaccurate, it’s consistently inaccurate and from multiple horses’ mouths at Intel. I can fairly easily devise a test that should show whether it’s actually the case or not.

        • chuckula
        • 2 years ago

        I’d love to see some AVX-512 tests make it to TR and since you have two Skylake X parts it would be very interesting to see the results.

        If it turns out that the 7900X has additional AVX-512 hardware in each core that’s not present in the lower-end chips, then perhaps they are only running half of the AVX-512 hardware in the 7900X and they could produce a major performance boost in the 7900X by getting the rest of the AVX-512 hardware working. So far they have not seen that occurring in most tests.

        Another computationally intensive benchmark that can use AVX-512 is the newest version of GIMPS (you need version 29.1 not the older 28.10). Most websites don’t actually know how to use it since they just show a power draw number that is completely divorced from the actual computational throughput, but proper testing could show if there is indeed a per-core difference in AVX-512 between different versions of Skylake X.

        • mcarson09
        • 2 years ago

        You mean run hwinfo64 and take a screenshot of the summary screen? All Xeons that use the same socket usually have all the same instruction sets. The only thing that seems to change is the cache sizes and core counts with the former being tied to the latter. The person this is giving out the bad info must work in PR, because that is usually where it comes from. Probably for the lack of understanding of the tech or the nuts and bolts of the current product line.

      • TheRazorsEdge
      • 2 years ago

      Nevermind, bad source.

      • ptsant
      • 2 years ago

      What does Agner Fog say?

    • TheRazorsEdge
    • 2 years ago

    If these were around when I got my 6700, I would easily have chosen the W-2123 or W-2125 equivalent.

    Especially at those prices—much better than their Skylake predecessors at launch, though we likely have to thank AMD for that.

      • blahsaysblah
      • 2 years ago

      I dont know. Intel hasn’t pushed out rock solid products at launch for many generations. That was with simpler product line. Now we have a gazillion chipsets and CPUs all releasing in same year.

        • jihadjoe
        • 2 years ago

        The new Coffee Lake desktop chips are looking solid though. I dunno if it’s the silly cache configuration or the mesh interconnect that fucked with Skylake-X, but Coffee Lake-S 6-core comes in at 95W and has 7700k IPC with good multi-core scaling.

        Makes me wonder why Intel decided to ‘fix’ something that wasn’t broken to begin with.

          • chuckula
          • 2 years ago

          Coffee lake is running the more standardized ringbus configuration and the ringbus is probably the most optimized configuration for chips up to about 12 – 16 cores or so with the advantages of the ringbus dropping as you add more cores.

          Intel most certainly did not design the mesh setup on Skylake X to produce the world’s best 6 core processor since Coffee Lake clearly takes that title outside of AVX-512 workloads. Instead, they designed the mesh to make the world’s best 28 core processor and as a platform that will scale to higher core counts in the future. An adverse side effect is that while the mesh scales up fairly well it doesn’t scale down as well to lower core counts.

            • NoOne ButMe
            • 2 years ago

            Agreed. Kind of surprised they didn’t do ring for the smaller die and mesh for larger, guess because it would take more engineering time/money…
            hope it wasn’t just a “we made the new thing so we use the new thing”

            • Beahmont
            • 2 years ago

            And yet for all of that, the actual interconnect times I’ve seen are still around the same as ThreadRipper CCX to CCX and drastically less than ThreadRipper chip to chip.

            I’ve seen reports that the big issue with the Mesh is not so much the speed of the interconnect, but the total amount of core to core cache snoops. Likely as a result the change to a victim cache L3 instead of an inclusive L3 cache. This would explain why even though ThreadRipper has higher latency in most of it’s snoops, it can turn in better performance because there are just fewer cache snoops to begin with.

            • smilingcrow
            • 2 years ago

            For certain DAW workloads multiple sources are showing that all Zeppelin based chips take a dive at lower latencies. I haven’t compared TR and Ryzen closely to see how they compare.

            • NoOne ButMe
            • 2 years ago

            Mesh gen1 versus Ring gen-5?6?7?

            But, Mesh is about fitting more cores on die.

            It probably was used here to “test” the Mesh in real world with how application users make it.

            And to avoid testing it on 10nm, having as a few new technologies when a node jump happens helps. Even if you have to re-implement the old ones nearly completely.

            If 10nm lives up to half of Intel’s hype for density improvement, than seeing 35-40 cores and 40-45 cores for the First/Second generation Xeon parts on it seems reasonable. With an upgraded and upgraded w/ real world feedback mesh! 🙂

            Food for though: A mesh also allows for “Better/easier” MCM or EMIB (think i got name right) possibly?

            • the
            • 2 years ago

            Nope. Intel adds a second ring once core count goes above 10 or so. Most they ever had on a single ring was 14 stops (note that memory controllers, PCIe controllers, GPU, and QPI interfaces count as a stop). The larger Xeons had two independent ring with a ring bridge for data to hop from one to the other.

            • chuckula
            • 2 years ago

            As I said, the ring configuration, and that could include two rings, is probably best [b<]up until a certain core count[/b<] and that's probably in the 12 - 16 core range depending on the setup. Two rings is still a ring bus configuration and there are substantial differences between that and a mesh. You have to remember that the "old" ring bus setup already scaled to 24 cores in the real world on the largest Broadwell E7 Xeon chips.

            • the
            • 2 years ago

            Adding more rings (or rings within rings which Ivy Bridge-EX used) is a compromise in scaling as there needs to be additional logic to bridge the rings. This weird things to latency and coherency protocols. Latency is no longer predictable dependent upon the direction you go on the ring as there are multiple paths when going from independent ring to independent ring over the bridges.

            Having multiple ring buses permits neat things like on-die NUMA configuration since each ring has a different access latency to the memory controller and cache to the other. Basically one half the chip sees the other half as if it were in another socket.

            I’ve outlined some of these details in a [url=https://techreport.com/forums/viewtopic.php?f=2&t=116378&p=1274725<]forum post a few years back[/url<]. I probably should update now that Broadwell-EX and Sky Lake-EP are out.

            • Mr Bill
            • 2 years ago

            [url=https://www.youtube.com/watch?v=kpRW8FZnwkU<]One Ring to Rule them All[/url<]?

    • demani
    • 2 years ago

    These appear to be the closest to Threadripper feature wise. Not pricewise though.

      • blahsaysblah
      • 2 years ago

      I think they’ve explicitly said that the 12 extra lanes were added for three native M.2/U.2/10Gb ports without having to give up the three native 16x slots.

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