Intel shows off 10-nm Cannon Lake wafer and talks process tech

Intel does fine work as a silicon designer, but its manufacturing technology is probably what truly sets the company apart from its competitors. The company held a technology and manufacturing event in Beijing on Monday to show off its latest advances in silicon manufacturing. The most interesting showpiece was a wafer of Cannon Lake silicon built using the company's next-generation 10-nm process technology. The company also talked about its plans to manufacture field-programmable gate arrays (FPGAs) on that process, and announced that it's shipping what it calls the world's first 64-layer 3D NAND for datacenter applications.

Stacy Smith, Intel's group president of manufacturing, poses with a 10-nm Cannon Lake wafer

Intel's senior fellow Mark Bohr reiterated that the company's 10-nm process is an entire generation ahead of the "10-nm" technologies developed by competitors in terms of transistor density and transistor performance, in its view. That's something the company has pointed out loudly in the past. Bohr said Intel's 10-nm tech has the "tightest transistor and metal pitches" and employs the company's "hyper scaling" approach first used in its 14-nm chips. The Cannon Lake wafer on display marked the first occasion that anyone outside of Intel has gotten a chance to see the product.

Intel didn't make any claims about the yields, functionality, or shipping timeline of the chips on its test wafer, however, and there may be a reason for that. Digitimes reported a rumor today that Intel has pushed retail availability of Cannon Lake chips back to the end of 2018. That rumor should be taken with a grain of salt, but if it's true, it would represent the third time Intel has delayed its 10-nm x86 CPUs.

Bohr also talked about his density metric proposal that could make comparisons between different manufacturers' process techs less confusing. The senior fellow noted that Intel continues to work on a low-power process for mobile applications called 22FFL. The company says its latest prototypes can operate at up to 2 GHz with "100x lower leakage" than its previous 22-nm General Purpose (22GP) tech.

Intel also plans to release "Falcon Mesa" FPGAs built on a 10-nm manufacturing technology that should offer reduced power consumption and better meet the demands of the company's datacenter customers. According to the company, these FPGAs build upon Intel's existing Stratix designs. Intel likewise announced that it's started shipping what it says is the first 64-layer 3D TLC NAND SSD suitable for use in datacenter applications. The company hopes that those SSDs will be "broadly available" by the end of 2017.

ARM fellow Gus Yeung displays a 10-nm wafer of Cortex-A75 CPUs

Last but not least, if you'll recall, Intel Custom Foundry announced a partnership with ARM back in August 2016 to accelerate development and implementation of ARM chips on Intel's 10-nm process tech. In Beijing, the silicon manufacturer showed off the first fruits of this partnership, a wafer of 10-nm ARM Cortex-A75 SoCs capable of clock speeds in excess of 3 GHz. The fact that Intel seems to be making its cutting-edge process technology available to fabless semiconductor companies could represent a shake-up to come in the mobile SoC market.

Comments closed
    • ronch
    • 3 years ago

    [quote<]Intel's senior fellow Mark Bohr reiterated that the company's 10-nm process is an entire generation ahead of the "10-nm" technologies developed by competitors in terms of transistor density and transistor performance, in its view. [/quote<] Well then, we'll just have to wait for [s<]GlobalFoundries[/s<] Samsung's 7nm process then!

    • ronch
    • 3 years ago

    I have much respect for [url=https://youtu.be/kJzf7jRqsAw<] Mark Bohr[/url<]. The guy is a true rocket (chip) scientist.

    • willmore
    • 3 years ago

    Look at the photo of that A75 test wafer. Zoom in and look at the size of the die. Looks like 9 die high and 11 wide. So, given it’s a 300mm wafer, that’s 33.3 by 27.27 for a die area of 909mm^2 That’s safely larger than any reticle that I’m aware of!

      • Kougar
      • 3 years ago

      Pretty sure just the dark squares are the actual logic, the rest of the wafer looks to be unused and left blank. ARM chips are pretty small things and one of those is about the size of the button on his shirt.

        • willmore
        • 3 years ago

        That’s a lot of wasted space on a test wafer.

          • the
          • 3 years ago

          Well it is a test wafer, not something being done for a full production run. The expectation is to get some working dies off of it for analysis and the discard once their research is complete. Maximizing the number of dies isn’t necessarily needed, especially if masking fewer of them speeds up the manufacturing process so that reaching the testing stage can be completed faster. A full wafer can take weeks/months to reach completion on a production line.

    • blastdoor
    • 3 years ago

    Allegedly TSMC will ship “7” nm next year. How does Bohr’s density metric rate that compared to Intel’s 10nm?

      • tsk
      • 3 years ago

      Intels 10nm seems to be twice as dense as TSMC’s 10nm, so I’d expect TSMC’s 7nm to be on par with Intels 10nm.
      [url<]https://images.anandtech.com/doci/11850/logicdensity.png[/url<]

        • psuedonymous
        • 3 years ago

        Going by [url=https://pbs.twimg.com/media/C8C7E2WXgAEJR9z.png:orig<]Wikichip's scale comparison[/url<], TSMC's 7nm is just behind Intel's 10nm.

          • tipoo
          • 3 years ago

          Yep. Pretty safe to still assume everyone’s advertised node is n-1 for Intel, for a few more years.

    • NTMBK
    • 3 years ago

    Apparently delayed until the end of 2018… [url<]http://www.digitimes.com/news/a20170920PD207.html[/url<]

      • chuckula
      • 3 years ago

      It’s almost like they thought of that:

      [quote<]Intel didn't make any claims about the yields, functionality, or shipping timeline of the chips on its test wafer, however, and there may be a reason for that. Digitimes reported a rumor today that Intel has pushed retail availability of Cannon Lake chips back to the end of 2018. That rumor should be taken with a grain of salt, but if it's true, it would represent the third time Intel has delayed its 10-nm x86 CPUs.[/quote<]

        • NTMBK
        • 3 years ago

        Whoops, shouldn’t have skimmed the article

    • chuckula
    • 3 years ago

    That Coffee is Non-Canonical.

    Having said that, apparently there’s a Coffee Cannon Stout:
    [url<]https://untappd.com/b/new-england-brewing-co-coffee-cannon-stout/1089632[/url<] Good enough for my purposes.

      • Redocbew
      • 3 years ago

      Beer to the rescue, again.

        • K-L-Waster
        • 3 years ago

        Is there a problem for which “more beer” is not the answer?

          • Pitabred
          • 3 years ago

          The only one that comes to mind is “too much beer”

            • Redocbew
            • 3 years ago

            But that doesn’t become a problem until later, and we all know the solution to that: more beer!

            • Neutronbeam
            • 3 years ago

            Your logic is unassailable.

    • Flying Fox
    • 3 years ago

    The title said Coffee, but the article said Cannon. So which lake is it?

      • morphine
      • 3 years ago

      Lake of Tears for the snafu on the headline. Thanks for the heads-up.

        • Neutronbeam
        • 3 years ago

        So… Cannon is canon?

          • morphine
          • 3 years ago

          *double facepalm*

    • godforsaken
    • 3 years ago

    Hey wayne, your headline reads coffee, while your story reads cannon.. otherwise keep up the good work

      • morphine
      • 3 years ago

      The lack of coffee at the TR HQ led to this Freudian slip. Our apologies, we have placed an order for more beans.

        • tipoo
        • 3 years ago

        And an order for canons

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