Samsung foundry train stops at 8-nm LPP before heading to EUV

Silicon manufacturing appears to be marching toward the era of extreme ultraviolet lithography (EUV), but Samsung's process train is making one last stop before pulling away from traditional litography and moving into the brave new world of short-wavelength exposures. The company has announced that it has completed qualification of its 8-nm "Low Power Plus" (LPP) process.

Samsung claims that chips built on the new tech offer 10% lower power consumption and a 10% reduction in die area compared to its 10-nm LPP process. The manufacturer expects adoption of 8-nm LPP chips in future mobile, cryptocurrency, and networking products.

Ryan Lee, VP of Foundry Marketing at Samsung Electronics, says the qualification process for 8-nm LPP is three months ahead of schedule. RK Chunduru, Senior VP of Samsung manufacturing partner Qualcomm, expects adoption of 8-nm LPP to be fast because the node "uses proven 10-nm process technology while providing better performance and scalability than current 10-nm-based products." The relatively conservative claims about power consumption and die area reductions suggest that the leap from 10-nm LPP to 8-nm LPP is a short one.

Samsung will present an update to its foundry roadmap at its Samsung Foundry Forum Europe event in Munich, Germany on October 18. The presentation will include information about 8-nm LPP availability and development of the next-generation 7-nm EUV process. The European event follows similar events earlier in the year in the US, South Korea, and Japan.

Comments closed
    • techguy
    • 2 years ago

    8nm offers a 10% area reduction over 10nm? In what world? 8^2 = 64, 10^2 = 100. That should be a 36% reduction. Either it’s not really 8nm or they don’t know how math works…

      • cmrcmk
      • 2 years ago

      Or there are other factors involved in transistor density that a simple <int>nm doesn’t reflect.

      • Jeff Kampman
      • 2 years ago

      “8-nm” is a marketing-approved method of denoting progress in foundry technology; it probably bears no relation to any meaningful physical characteristic of the process. If we go by Samsung’s description this is at best a tenth-shrink, not even a half- or quarter-shrink.

        • tsk
        • 2 years ago

        I find it a bit confusing though, who are they marketing 8nm to?
        Their partners who’s deciding between Samsung or TSMC?
        Surely when Qualcomm picks a foundry for their chips there’s more to it than Samsung 8nm vs TSMC 10nm, so Samsung wins cause 8 is better than 10.

          • Jeff Kampman
          • 2 years ago

          Investors.

        • freebird
        • 2 years ago

        Samsung HAD to announce something… since they’re moving to 7nm ONLY WITH EUV, they won’t have 7nm as early as TSMC or GF. If they don’t have something with a comparatively small size people will “think” they are falling behind… ;D

        In addition, Samsung’s LPP is Low power PLUS… so this will probably be limited to phones and such.

        But we all know what Tony the Tiger says about lower nanometer processes….

        “They’re grrrrrreat!”

    • DavidC1
    • 2 years ago

    The nm metric is changing to a point where it will eventually have the same meaning as the designation “7700K” on a Core i7 7700K processor.

    • ronch
    • 2 years ago

    “Nonsense! That’s not true 8nm!”

    – Mark Bohr, Intel

    • DeadOfKnight
    • 2 years ago

    EUV is a myth, just like 450mm wafers. End of the road, I’m afraid.

      • Stonebender
      • 2 years ago

      I talk to ASML engineers everyday. EUV actually is finally here for the most part. The big hurdle was getting enough power to the tool to get a descent water throughput rate, and it appears they’ve figured it out. 450mm wafers however…

        • smilingcrow
        • 2 years ago

        The cost of the cheese and pickle plus the calorific content makes 45cm wafers unfeasible except for the food equivalent of over-clocking; food eating contests.

          • derFunkenstein
          • 2 years ago

          all you need is a sturdy, cheese-bearing cracker.

            • Mr Bill
            • 2 years ago

            And an after dinner mint, they’re wafer thin!

      • NoOne ButMe
      • 2 years ago

      450mm wafers and EUV target the same problem in different ways.
      The positives and negatives of 450mm wafers were to slanted towards negatives to move forward.
      EUV seems to have more positives than negatives.

        • Stonebender
        • 2 years ago

        Really? How does switching to 450mm wafers help you move to a smaller process node? It’s not even remotely the same problem.

          • DavidC1
          • 2 years ago

          Stonebender: It does, indirectly.

          450mm wafers mean you can yield many more functional dies per wafer, and the cost per die can be reduced because there’s less steps you do per mm2. It’ll be easier to make dies that scratches the limits of reticle size, meaning even higher performance chips are possible.

          The increased revenue due to those factors allow smaller process nodes to be supported, because frankly, costs for new nodes are insane, and every step to help reduce costs will allow Moore’s Law to continue for longer periods of time.

            • Stonebender
            • 2 years ago

            Do you have any idea how monumentally expensive it would be to switch a factory to 450mm wafers? Sure on paper 450mm wafers are great, but then the reality hits. First of all, they would be extremely heavy, so you’d have to move from 25 wafer foups down to something like 10. Then, how many machines exist that can internally support 450mm wafers? How many would you have to replace? How much downtime would you have while switching over every wafer stocker and foup transport system in the fab? This doesn’t even get into the process side disadvantages.

            • DeadOfKnight
            • 2 years ago

            Pretty sure Intel has built like 2 new fabs since announcing their move to 450mm wafers. Might have been a thing, but it’s not.

            • NoOne ButMe
            • 2 years ago

            450mm is dead currently, and has been for a while. Intel is not making any fabs for 450mm wafers.
            It’s why Intel has talked up Hyperscaling.

            • NoOne ButMe
            • 2 years ago

            which is why 450mm wafers were meant to be something you do as you shrink nodes…. from 14nm to 10nm, you’re going to need all new equipment anyways.

            So instead of 300mm equipment, you would buy the 450mm equipment, which once developed, would almost certainly be < 2.25x the cost of 300mm equipment.

            • Stonebender
            • 2 years ago

            You don’t need new equipment though. Not really. 10nm is still using the same 194nm lasers that ASML has been using for years now. The scanners are essentially new versions of the same machines, in fact some of the 14nm machines are being upgraded to run the 10nm process. The rest of the fab can use the same machines they’ve been using for the most part, as they are whole wafer processes and aren’t affected by node shrinks.

          • NoOne ButMe
          • 2 years ago

          It’s all about cost. You notice in Intel’s investor call where they brought up higher-scaling they compared it as beneficial as 450mm wafers? It’s because at the end of the day, node shrinks are about cost.

          If the cost decreases more, that means more customers, so foundry can throw more money at shrinking the node.

          More money faster means a faster shrink, generally speaking.

    • smilingcrow
    • 2 years ago

    10% only! I don’t get out of bed for such trifles.

    • Wirko
    • 2 years ago

    That nanometric metric had little value before and completely lost it now. It’s time to start talking about MTr/mm2 primarily.

      • NoOne ButMe
      • 2 years ago

      yeah, MTr/mm2 on shipping products… unless you’re Intel, in which case ignore shipping products and only theoretical ^_^

        • JustAnEngineer
        • 2 years ago

        Do you mean Intel products like the theoretical (but not shipping) Core i7-8700K?

          • strangerguy
          • 2 years ago

          Intel has the process that clocks the highest, but it’s not even remotely the densest one anymore in a current process gen shipping product. Skylake was the first gen that they never disclosed the transistor count, but my guesstimate says the quad version couldn’t be any more than 2 billion, more like 1.6 billion from historical trends and their 14nm++ for CFL is said to have even larger gates for better electrical characteristics.

          -Skylake GT2 4C: 2 billion transistors / 122 mm^2 = 16.4 million transistors/mm^2
          -Apple A11: 4.3 billion transistors / 90 mm^2 = 47.8 million transistors/mm^2

            • smilingcrow
            • 2 years ago

            When making comparisons between processes it’s good to keep in mind the major differences between those designed for 5W and under chips and those aimed at 90W plus chips as they are noticeanly different.
            Another reason why comparisons are difficult.

            • NoOne ButMe
            • 2 years ago

            So compare 14nm Atom (like we could ever get those numbers sadly) to 14nm Qualcomm/Samsung/Apple/MediaTek.

            • Waco
            • 2 years ago

            Those are still very different products.

            The only true way to compare would be to have all competitors fab a specific design – IE: 1 MB SRAM with a very specific interface and power/clock targets.

      • Mr Bill
      • 2 years ago

      Hasn’t Intel always been spreading out critical circuit blocks so they can clock faster?

    • Wirko
    • 2 years ago

    That nanometric metric had little value before and completely lost it now. It’s time to start talking about MTr/mm2 primarily.

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