Updated: Cannon Lake Core i3-8121U may support AVX-512 after all

Update 5/16/2018 5:55 PM: Intel has confirmed that the Core i3-8121U supports AVX-512 instructions and has added that information to the ARK database. Our original story continues below.

When Intel's Cannon Lake Core i3-8121U appeared in the company's ARK database yesterday, the chip's entry didn't suggest any support for AVX-512 instructions—an expected feature of the next-generation microarchitecture. That entry may be incomplete, however. CPU detective InstLatX64 has obtained a CPUID dump for the chip from a Lenovo Ideapad 330-15ICN with the i3-8121U inside, and the chip does appear to offer AVX-512 support.

According to the CPUID dump, Cannon Lake supports the Foundation (F), Conflict Detection (CD), Byte and Word (BW), Doubleword and Quadword (DQ), and Vector Length (VL) subsets of the AVX-512 instruction set that are already implemented by Skylake Server chips, along with two new support levels: Integer Fused Multiply Add (IFMA) and Vector Byte Manipulation Instructions (VBMI).

Cannon Lake also appears to be the first Intel core to support Intel's SHA Extensions for accelerated processing of certain encryption operations. AMD's Ryzen processors were the first desktop processors to implement SHA Extensions. InstLatX64 notes that the i3-8121U does not support Intel's Software Guard Extensions for hardened execution of compatible programs, however. In any case, we've asked Intel for confirmation of AVX-512 instruction support on Cannon Lake, and we'll update our coverage when we hear back.

Comments closed
    • DavidC1
    • 1 year ago

    It may be 1x AVX-512 support by ganging up 2x AVX-256 units. That brings the benefits of a better, expanded instruction set without the costs of the extra 512-bit SIMD. Wasn’t AVX-512 supposed to make previously unvectorizable instructions vectorizable?

      • Klimax
      • 1 year ago

      Correct. It is done through masking register and two extra forms of instructions. (Mask write-through and zero-mask) Most important though is VL version of original AVX512 instructions. (They are not as bandwidth bound nor lowering frequency that much (on par with AVX) while offering some very interesting and long missed instructions. (like variable rotation)

    • the
    • 1 year ago

    Weird. Things are pointed toward a third iteration of the Sky Lake leanage:
    Initial consumer with 256 KB L2 and ring bus
    SP for sever with AVX-512, 1 MB L2 and tile interconnect
    Cannon Lake with AVX-512, 256 KB L2 and ring connect (maybe?)

    The Cannon Lake core is the odd one out as it’d require both a shrink and a redesigned of SIMD functionality. It would have made more sense to shrink the Sky Lake-SP design to maintain consistency.

      • chuckula
      • 1 year ago

      Expect to see more of this in the future. The mesh interconnect and cache architecture of the big Xeon parts is designed to overcome bottlenecks that were beginning to show up as Broadwell went past 20 cores. However, in the consumer space (and by “consumer” I include even a 16-core high-end desktop/workstation chip) that architecture can actually be somewhat substandard since it’s designed to scale up and not down.

        • the
        • 1 year ago

        The thing is that more than just CPUs sit on the on-die coherent interconnect. Right now there are PCIe controllers, memory controllers, QPI/UPI links and the integrated GPU. Additional accelerators are on their way to the on-die interconnect as well (FPGA, high speed networking) Between consumer and server, keeping the CPU, memory and PCIe controllers in sync saves Intel development costs and time.

        Intel started to feel the impact of overly large ring buses since Ivy Bridge EX as that was when they started to supplement the number of rings in the system which had twenty functional units with ring stops.

        I would predict that Ice Lake unified everything again.

          • Beahmont
          • 1 year ago

          Not unless they can get the relay speed of the mesh up significantly. The minimum transfer times are horrible though the maximum transfer times are actually fairly good. But on a consumer part the mesh is simply more expensive and provides a negative value to the final product.

          Intel can’t just simplify the design to save money at the cost of performance in the beginning stages of a performance war with AMD. At least they can’t if they want to win.

          • DavidC1
          • 1 year ago

          “I would predict that Ice Lake unified everything again.”

          Rumors suggest a *further* divergence between client and server lines. Sapphire Rapids generation is the server chip that is supposed to highlight the switch.

          Mesh is much more complex than ring bus by nature which is why it has problems with performance on the high-clocked client parts. It’s at the moment no problem for server because server parts clock much lower. It has to do with relative latency. 3GHz Mesh is ok on a 3.4GHz server part, but quite slow on a 5GHz client one.

          Unlikely we’ll see unification happen as we’re really limited by clock speeds and, process scaling drastically slowing.

    • ig0012
    • 1 year ago

    50% higher SFFT score may mean that i3-8121U indeed supports AVX-512

    [url<]https://browser.geekbench.com/v4/cpu/compare/7582239?baseline=6246666[/url<]

      • chuckula
      • 1 year ago

      I’d like to see how it does in [url=http://www.numberworld.org/y-cruncher/<]Y-cruncher[/url<] too.

    • chuckula
    • 1 year ago

    OK! Now that we have confirmed that Cannon Lake supports these instructions I want everyone to throw out page 1 of your instructions where we bashed Intel for failing to put AVX-512 in Cannon Lake and instead use page 2 where we call these features useless because they don’t make Cinebench faster.

    No going off script here!

      • The Egg
      • 1 year ago

      Poor Intel. They’ll have to fill out a Hurt Feelings Report after all this.

        • chuckula
        • 1 year ago

        Intel can’t fill out the HFR because AMD took the last copy yesterday.

          • derFunkenstein
          • 1 year ago

          Well that’s on their HR department. They should always know to photocopy the last one a minimum of 10x before giving it to an employee.

            • psuedonymous
            • 1 year ago

            “10nm has been shipping since 2017-”
            “Been shipping?! I had to go down to the cellar to find it!”
            “That’s the shipping department.”
            “With a torch!”
            “Ah, well, the lights had probably gone.”
            “So had the stairs.”
            “But look, you found 10nm, didn’t you?”
            “Yes, yes I did. It was at the bottom of a locked filing cabinet stuck in a disused lavatory with a sign on the door saying ‘Beware of the Leopard.”

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