Intel announced that its first Xeon Scalable processor with an integrated FPGA is being made available to select customers. The Xeon Scalable 6138P includes an Arria 10 GX 1150 FPGA on package that's connected to the CPU die using Intel's Ultra Path Interconnect (UPI). According to Intel, UPI offers these chips coherent and direct access to data in the processor or FPGA caches and in main memory without the overhead of direct memory access or data replication.
The Arria 10 GX 1150 is the beefiest FPGA in its family, with 1,150,000 programmable logic elements, 427,200 adaptive logic modules for efficiently constructing certain LUTs, 96 17.4-Gbps transceivers, and 768 pins of GPIO, among other features. Intel didn't specify the Xeon chip that accompanies the Arria 10 GX 1150, but the standard Gold 6138 is a 20-core, 40-thread chip with a 2-GHz base clock and a 3.7-GHz Turbo frequency in a 125-W TDP.
As an example of how the Xeon 6138P might be used by customers, Intel created a virtual switching reference platform that uses the FPGA portion of the chip for infrastructure dataplane switching while the CPU runs its usual applications or virtual machines. Offloading the software-defined networking load to the FPGA apparently offers better performance than asking the CPU alone to handle both workloads, as we might expect.
Intel also notes that the 6138P is compatible with the Open Virtual Switch software-defined multilayer switch for VM environments, and it claims that an OVS implementation running on this chip offers a 3.2X throughput improvement and half the latency of a non-FPGA-accelerated workload for twice the virtual machines that a CPU alone can run.
Intel says Fujitsu is its lead partner for the Xeon 6138P, and that the firm plans to pair its own reliability, availability, and serviceability (RAS) special sauce with Xeon 6138P processors for software-defined network infrastructure equipment. Fujitsu will be demonstrating its implementation of the 6138P at its Fujitsu Forum this week in Tokyo.