David Kanter dissects Intel’s plans for Optane Persistent Memory

Intel's Optane Persistent Memory sticks put 3D Xpoint memory chips in DIMM slots. While that may sound straightforward enough, the shift from DRAM to higher-density non-volatile stuff around server sockets could effect wide-ranging changes in the data center, and those potential shifts are only beginning to take shape.

Thankfully, David Kanter has given those potential changes a more solid form by diving into Optane Persistent Memory, also known by the code-name Apache Pass. He's outlined the implications of this technology for performance and software developers, as well as the open questions and potential pitfalls still remaining ahead of the product's broad launch. If you want to get abreast of those issues, you'd do well to give David's article a read.

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    • Bauxite
    • 1 year ago

    Yet to see any explanation how the memory controller will handle mixed latency DIMMs in the same banks/channels. How is that solved in the next cpus, or is intel just going to gloss over a “little” detail?

    Right now with every x86 IMC your CAS etc DIMM timings are uniform and run at the lowest common denominator. OS/drivers/software have nothing to do with this. Optane is fun stuff but still over a order of magnitude higher latency than regular DDR#.

    A lot bigger ram pool is nice but may not be worth running the regular stuff extra slow depending on your workload. See the difference even between speed grades of DDR4 (speed/CAS = ns) in various sensitive benchmarks. I’m not even sure current commodity modules can run at extremely high CAS correctly.

      • chuckula
      • 1 year ago

      [quote<]Yet to see any explanation how the memory controller will handle mixed latency DIMMs in the same banks/channels. How is that solved in the next cpus, or is intel just going to gloss over a "little" detail? [/quote<] You're right! We never thought of that. All Optane products are officially canceled and we're going out of business!

        • kuraegomon
        • 1 year ago

        You may not always be the Chuck we want, but there are times when you’re the Chuck we need. This is one of those times – +3 bestowed :’-D

          • blastdoor
          • 1 year ago

          Ditto

        • freebird
        • 1 year ago

        Well, apparently, Intel CANNOT or will not answer many simple questions about 3DXP.
        Seeing how server chips that support these VERY expensive DIMMs will also most likely be
        very expensive these really are questions that should ALREADY have answers.

        From an Anandtech article:
        [url<]https://www.anandtech.com/show/12826/intel-persistent-memory-event-live-blog[/url<] 02:56PM EDT - OK Q&A over, here are the questions and results 02:56PM EDT - Q) Do the DIMMs require next gen CPUs? A) Yes 02:57PM EDT - Q) You mentioned Intel will be revenue shipping for 2018. Will ecosystem partners be shipping systems in 2018? A) We expect systems to be shipping in 2018, but the details of specific customers will be up to them 02:57PM EDT - Q) What is Crystal Ridge? A) Crystal Ridge is the top level family of persistent memory parts, of which Apache Pass is a member 02:58PM EDT - Q) It was mentioned about DDR4 pin compatibility with the DIMMs. Can users mix and match the DIMMs on individual channels, or will there be dedicated channels? A) Not disclosed at this time. 02:59PM EDT - Q) One of the slides had a Xeon Platinum logo. Will the DIMMs only work on Xeon Platinum? A) Not disclosed at this time. We just showed pairing the best with the best 02:59PM EDT - Q) Will there be a DIMM writes per day? A) Not disclosed at this time. But DIMMs will be operational for the lifetime of the DIMM 03:00PM EDT - Q) What is the power draw of the Optane DIMM compared to regular DIMMs? A) Not disclosed at this time. 03:00PM EDT - Q) Does this mean the memory limits of future Xeons are being increased? A) Not disclosed at this time. 03:00PM EDT - Q) Will all future Xeons support the Optane DIMMs? A) Not disclosed at this time. 03:00PM EDT - Q) Clock speeds of the DIMMs? A) Standard DDR4 speeds. Other details not disclosed. 03:01PM EDT - Q) Will the QLC NAND adhere to JEDEC data retention. A) Not disclosed at this time.

          • chuckula
          • 1 year ago

          Yes and how many specific answers did Lisa Su give about Vega 20 at AMD’s press demo?

          You really need some perspective.

            • moose17145
            • 1 year ago

            Just because Company A does not answer many questions that people want answers to and SHOULD have answers to before they spend their hard earned money, does not mean that it is alright for Company B to do the same thing…

            Talk about needing some perspective indeed…

            • freebird
            • 1 year ago

            Perspective? Who’s talking about Vega 20???
            You.

            I could’ve sworn this article and comments were about 3DXP?

            Personally, I don’t really give a darn about Vega 20 because it is for the compute crowd. I would imagine AMD/Lisa Su or whoever at AMD is going to have to give demos and info about Vega 20 if they want people to buy it, correct?

            So quit changing the subject (from 3DXP to Vega 20) like you so often like to do…

      • Buub
      • 1 year ago

      I didn’t look closely enough to confirm this, but I expect that the memory controller (and DIMM slots) for the DRAM and the memory controller for the Optane memory will be entirely separate. It’s not like you won’t need both.

      • moose17145
      • 1 year ago

      Not exactly sure why you are being chastised for asking a perfectly legitimate question.

      Apparently people on this TECH SITE do not want to know how this stuff operates for some reason…

      • cmrcmk
      • 1 year ago

      My assumption is that using Optane DIMMs will require the server to dedicate one to four memory channels to it with the rest being available for standard RAM. It shouldn’t be too difficult for Intel to allow the six memory channels in modern Xeons to be partitioned like that with fully independent clock speed and latency from the “normal” channels.

      I haven’t read anything that speaks directly to this idea but I have read several articles implying interleaving Optane and DDR on the same channel and that just doesn’t make sense to my amateur EE brain. Not that Intel couldn’t, it just seems like it would be way more work to have each channel handle both media simultaneously and thus wouldn’t happen without a really good reason.

      • Waco
      • 1 year ago

      If you go spec out a machine with NVDIMMs there’s a requirement to fill out channels with similar types of memory. IE: you dedicate channels to NVDIMMs and they have different speeds/timings.

      Short answer: they thought of this, it’s exactly what everyone expected.

    • chuckula
    • 1 year ago

    The persistent byte-level access is really what sets these DIMMs apart from a fast NVME drive, and even an Optane NVME drive. In the configurations that Intel has shown each Optane DIMM is still paired with a standard RAM DIMM, so these things are not mean to completely supplant standard RAM but are instead there to provide a high-speed store for persistent data that you can’t get with a regular storage solution, even a fast one.

      • Amiga500+
      • 1 year ago

      You’d think that Intel will be looking at bringing the Optane DIMMs into the Smart Response framework.

      It’d certainly be the easiest fit into the current software ecosystem.

      Whether that means they also require asynchronous channels on their memory controller (as queried already) is another matter. That shouldn’t be an impossible technical hurdle to overcome – CPU (or even a simplistic northbridge) detects whether channel is Optane or RAM and the memory controller/motherboard tiers it accordingly.

      We’ve already seen CPUs with DDR2 and DDR3 memory controllers – so its already been half done.

    • Mr Bill
    • 1 year ago

    [quote<]The endurance of the initial P4800X is 30 drive-writes per day (DWPD), roughly 2X better than NAND-based SSDs.[/quote<]... For what total interval of days?

      • chuckula
      • 1 year ago

      Optane, like the Enterprise, is on a 5 year mission.

    • blastdoor
    • 1 year ago

    [quote<]In a PC or server, paging code from NAND flash is fairly fast, but XIP with 3DXP DIMMs could eliminate or hide the latency of paging altogether.[/quote<] I've been thinking that the ability to hide latency from paging might make this technology appealing in smartphones or tablets. Apple has always been criticized for under provisioning RAM, but they claim they do it to save power. So how about combine 2GB of RAM with 8 GB of 3DXP?

      • Goty
      • 1 year ago

      Kanter suggests that the power consumption of the OPM modules might be comparably higher than a DIMM, so there might not be that much power savings to be had.

        • blastdoor
        • 1 year ago

        Is the key — what fraction of the time is it being used?

        Perhaps I’ve misunderstood, but I thought an advantage of 3DXP is that it doesn’t lose data when it loses power, which seems to suggest that it could be powered down a large fraction of the time. But is there an issue that if it’s powered down, then the latency advantage disappears? <edit> — in other words, what’s the ‘boot time’ for 3DXP?

    • psuedonymous
    • 1 year ago

    Does anyone get the feeling that Optane will eventually end up on the end of a new interconnect (i.e. not NVME over PCIe or DDR)? PCIe is a bottleneck for memory that can be arbitrarily row & column accessed, but DDR is tuned for much tighter timings than 3DXpoint is likely to achieve for the next few generations. Plus its presence on the desktop makes the most sense as an implicit transparent storage cache rather than its explicit use as Optane Memory (or as a dedicated drive for most due to expense at capacity) so having a custom interface is not a detriment there. Maybe an older DDR (or even SDR) standard or a variant on HMC’s interface might turn up on future CPUs.

      • uni-mitation
      • 1 year ago

      [quote<] PCIe is a bottleneck for memory that can be arbitrarily row & column accessed, but DDR is tuned for much tighter timings than 3DXpoint is likely to achieve for the next few generations.[/quote<] 1- From the article: [quote<] For 3DXP to become a viable complement to DRAM and NAND, it requires a different system and software architecture, which Intel recently announced. As widely expected, Intel will offer 3DXP-based DIMMs (previously codenamed Apache Pass) that use a low-latency DDR4 memory interface, rather than PCIe [/quote<] 1.1- It talks about that new software to exploit this new hardware. It is a good read. uni-mitation

        • psuedonymous
        • 1 year ago

        I read the article, and Apache Pass is [b<]NOT[/b<] intended for transparent implicit caching. It at best [i<]can[/i<] be used as an opaque explicit cache (which would be a waste), but for the most part it is meant to be an explicit store (as in the database example) below main memory, rather than a cache a level above the backing store. DDR4 is used as the interface because it is already there, but it is hardly an ideal interface. It's overkill for Optane in terms of performance, inefficient (waste of power and die space), and trying to hammer out the timing issues is what has delayed Apache Pass for so long.

      • NTMBK
      • 1 year ago

      If you’re using it as a transparent storage cache, then you have to hide the fact that it’s byte-addressable and treat it the same as your storage device.

        • psuedonymous
        • 1 year ago

        That’s at the logical level (that’s what ‘transparent cache’ [i<]means[/i<]), at the hardware level you want to take advantage of 3D Xpoint's actually unique capabilities or you miss out on most of the benefits.

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