Intel's "design teams and design resources are well stocked, so they can do a shrink early or do a dual-core (chip) early. They have a lot of leeway that would stress out a Sparc development team," Eunice said, referring to shrinking the size of components on a chip and to Sun Microsystems' UltraSparc processor.The new Itanium schedule calls for Madison, a version of the Itanium 2 with 6MB of L3 cache, to debut this summer. Madison will be followed by Deerfield, a low-power version of the Itanium 2 designed for high-density servers. In 2004, we'll see a version of Madison with 9MB of L3 cache, which will be followed by Montecito in 2005. Montecito is particularly interesting because it will feature two full processor cores in the same chip package. Originally, Intel had dual core chips scheduled for 2007, but they're optimistic that their fabs can crank out 0.09-micron dual core chips a couple of years early.
Intel's accelerated plans for future Itanium processors are certainly bolder than they were before, and it will be particularly interesting to see Madison face off against AMD's Opteron this summer. An accelerated roadmap for Intel's server-class Itaniums may also indicate that the chip giant has accelerated plans to migrate Itanium technology to desktop processors. Then again, that eventual migration may be so far off in the distance that even an accelerated roadmap would keep it well beyond the horizon.