The audience keenly listened as Meyerson told how a dramatic rise in power density, brought about by the traditional brute scaling of process technology dictated by Moore's Law, has already yielded silicon that could iron a pair of pants and is on a curve heading toward supernova.The article suggests that design-level innovations may have to replace die shrinks as the big scheduled changes on chipmakers' roadmaps. There's also talk about the need for closer collaboration between design engineers and process engineers, which may be especially dicey for fabless semiconductor companies with aggressive schedules, like ATI and NVIDIA.
In other words, physics is getting ugly. The days of relatively generous amounts of gate oxides, on the order of say 30 angstroms, have given way to the angst of dealing with less than 10 angstroms, making brute scaling nearly impossible. That's why some in the industry, including Meyerson, believe that classical CMOS scaling is no longer possible.