Future Athlon 64s to include SSE3 support

The next revision of AMD’s Hammer CPU core will include SSE3 support, among other new features, according to this talk given by Kevin McGrath, AMD’s chief Hammer architect, at Stanford University. Here’s the key slide from the presentation:

The video source isn’t terribly high res, unfortunately. McGrath describes new features added to Hammer since its launch, but like the slide, he’s a little fuzzy about when various changes have been implemented. Obviously, some of the features haven’t yet arrived, though.

The enhancements include power reductions (gained by using slow but less leaky transistors in non-critical paths) and speed improvements (by using fast but leaky transistors in critical paths). Also, the processor halt and stopclock states have been improved, reducing some unnecessary work previously conducted during these states, resulting in a savings of several hundred milliwatts. Like the Pentium 4, future Hammer chips will feature on-die thermal throttling to cool themselves down if certain temperature limits are reached.

Performance-wise, the big news is the addition of SSE3 instructions, which accelerate a number of different types of computation, including video encoding, scientific computing, and software graphics vertex shaders. (For more on SSE3, see our Prescott review.) Beyond SSE3, the updated Hammer core will convert the LEA instruction, under certain circumstances, into an ADD instruction, which has only a single cycle of latency. AMD’s design mavens have also added additional write-combining buffers to the chip, so it can combine up to four streams of non-cacheable writes, up from two. Hammer’s data prefetch has been improved, as well.

The memory controller has DDR400 support, as we all know, and an improved open page policy.

I believe we’ll see the biggest changes implemented in the upcoming 90nm die shrink of the Hammer core, but like I said, he seems fuzzy on the timing, and some may be available sooner or in current chip revs. (Thanks Stefan Neef, who found out about the presentation via this story at c’t.)

Comments closed
    • DarthVegas
    • 14 years ago

    r[Yea,what he said!>>>>>>>:)

    • moran
    • 16 years ago

    Sounds like AMD and Intel have done some sort of deal ie sse3 for x86_64

    • wierdo
    • 16 years ago

    On the contrary, I think AMD did a good job with SSE2, they addressed it AFTER software started seriously taking advantage of it, but that’s just imho.

    • wierdo
    • 16 years ago

    On the contrary, I think AMD did a good job with SSE2, they addressed it AFTER software started seriously taking advantage of it, but that’s just imho.

    • Decelerate
    • 16 years ago

    When they say next version, do they mean 3700+ and on
    or
    Socket 939/3700+ and on? (as in:does a 3000+ socket 939 count as next version?)

      • Ryszard
      • 16 years ago

      Socket 939 starts with three chips. Model 3400+, Model 3700+ and limited availability of FX-53.

      Socket 754’s new 3400+ that arrives when Socket 939 launches will carry the CG core stepping and will be different to the existing 1MB Socket 754 Model 3400+ (2.4GHz, 512KB L2 instead of 2.2GHz, 1MB).

      If the CG stepping carries some or all of the new enhancements, they all arrive quite soon (end of this month).

      Rys

        • Decelerate
        • 16 years ago

        Thanks for the heads up.

        I don’t like how AMD backed out of 1MB Cache 2 to 512k/DualChan xcept for FX.

        Imo 1MB Cache 2 should’ve been the new standard for mainstream desktop (512k for the value market)

    • atidriverssuck
    • 16 years ago

    power reductions, speed improvements and SSE3 support. Can’t complain if they deliver these as they say. Gotta love competition.

    • slymaster
    • 16 years ago

    The quick implementation of SSE3 will help negate a possible advantage that Intel would have once SSE3 enabled apps start appearing. SSE2 was in use for too long before AMD supported it.

    • Johnny Rotten
    • 16 years ago

    As I understand the memory controller ‘tuning’ has been implemented in the new stepping of the A64 (to start with the A64 3700+).

    Sure would be nice if the prefetch improvements were in there too (wishful thinking I suspect)

    • data8504
    • 16 years ago

    It’s good that AMD isn’t making the same mistake with SSE2 that they did with SSE3. Back in the day of the original Pentium 4, it was a sucky performer — and AMD saw no need to include SSE2 until it was too late, and Hammer was so close that they decided to just hold off.

    Who knows if SSE3 is going to be a big thing…

    • MagerValp
    • 16 years ago

    But LEA *[

      • sayler
      • 16 years ago

      LEA is already an ADD, but is handled by a part of the core with a slightly higher latency than a straight ADD. The idea is to speed up code that happens to use LEA like an ADD (and there are optimization techniques that do this, as far as I know).

    • Sargent Duck
    • 16 years ago

    I think Intel is going to take quite a beating this round. They better hope they can cool the Prescott down and crank that beast to some insane clockspeeds if they hope to have a chance in getting a performance crown.

    • dalamar70
    • 16 years ago

    Are there any SSE3-enabled applications (or compilers) available yet?

      • Stefan
      • 16 years ago

      The newest iteration of the gcc compiler does support SSE3 (although not verctorization, so don’t hold your breath), as does (obviously) Intel’s newest. Dunno about Microsoft.

      Edit:
      Also, Codeplay’s “VectorC” does support SSE3 _[

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