Celeron II follow-up action
Looks like our little effort at stirring the pot over Celeron II performance throttling
woke up the big guys this week. The boy wonder weighed in with his thoughts on the subject
, articulating elegantly what some of you were getting at in your comments on the issue. He uses WCPUID to spot the new Celeron's cache latency value (2 for the Celeron, zero for the PIII) and its L2 cache capabilities (4-way set associative on the Celeron, 8-way for the PIII). So much for the theory that the Celeron IIs are discarded Pentium IIIs. Intel has intentionally slowed down these chips, so that the PIII can continue to command its price premiums. So the new "Celermines" will have to play 386SX to the PIII's 386DX.
Not long after the boy wonder's contribution, the folks at the FiringSquad went and benchmarked a Celeron and PIII at the same bus and clock speeds, with and without the L2 cache disabled. (I wonder where they got that idea, hmm?) As expected, the CII and PIII performed identically once the L2 caches were off. So it really is all about the L2 cache. Consider this one settled, folks.
Q: What's the difference between TR and the FiringSquad?
A: We link them when they do something interesting.