We quizzed Weber on several key points about future microprocessor directions, including the question of thread-level parallelism (as in multi-core CPUs) versus more traditional instruction-level parallelism. We also got his take on the approach used by the Cell processor, and we gathered a number of hints about what future AMD CPU cores might look like. This last bit was perhaps the most interesting, because Weber gave us a sense of where AMD might possibly be going with its next generation of CPUs. Among the enhancements mentioned were possible shared L3 caches, instruction combining a la the Pentium M's micro-ops fusion, and better prefetching of data into cache. Weber said he doesn't see the need for a wider execution core than the current K8, although he does like the possibility of better branch prediction and possibly deeper pipelines and higher clock frequencies. However, he was clear that the primary emphasis for AMD going forward will likely be thread-level parallelism, with linear performance increases per CPU core taking a back seat.
We also got some interesting dirt from AMD's mobile folks on the Turion 64, which has been something of a mystery since its launch. As we'd thought, the current Turion is not significantly changed at the logic level; it's basically a K8 core that includes the ability to enter a deeper C3 sleep state. AMD has tuned the Turion for lower power consumption by tweaking its fab process, using transistors that switch slower but have less current leakage. That puts the Turion's power consumption and heat production at a place where five-pound notebooks can use it, but not the really small and sexy types that weigh four pounds or less. In the future, though, AMD may produce a more targeted variant of its CPU technology for mobile applications. Apparently, AMD has engineering resources in Japan working on a product definition for such a chip. That means everything is very preliminary, of course, but AMD may be moving in that direction in the future.