Intel reveals details of new CPU design

IDF — On the heels of Intel’s announcement of a single, common CPU architecture intended to drive its mobile, desktop, and server platforms, the company has divulged additional details of that microarchitecture. This dual-core CPU design will, as we’ve reported, support an array of Intel technologies, including 64-bit EM64T compatibility, virtualization, enhanced security, and active management capabilities. Intel says the new chips will deliver big improvements in performance per watt, especially compared to its Netburst-based offerings.

At 14 stages, the main pipeline will be a little bit longer than current Pentium M processors. The cores will be a wider, more parallel design capable of issuing, executing, and retiring four instructions at once. (Current x86 processors are generally three-issue.) The CPU will, of course, feature out-of-order instruction execution and will also have deeper buffers than current Intel processors. These design changes should give the new architecture significantly more performance per clock, and somewhat consequently, higher performance per watt.

Unlike Intel’s current dual-core CPU designs, which don’t really share resources or communicate with one another except over the front-side bus, this new design looks to be a much more intentionally multicore design. The on-die L2 cache will be shared between the two cores, and Intel says the relative bandwidth per core will be higher than its current chips. L2 cache size is widely scalable to different sizes for different products. The L1 caches will remain separate and tied to a specific core, but the CPU will be able to transfer data directly from one core’s L1 cache to another. Naturally, these CPUs will thus have two cores on a single die.

The first implementation of the architecture will not include Hyper-Threading, but Intel (somewhat cryptically) says to expect additional threads over time. I don’t believe that means HT capability will be built into silicon but not initially made active, because Intel expressly cited transistor budget as a reason for excluding HT.

On the memory front, the new architecture is slated to have the ever-present “improved pre-fetch” of data into cache, and it will also include what Intel calls “memory disambiguation.” That sounds an awful lot like a NUMA arrangement similar to what’s found on AMD’s Opteron, but I don’t believe it is. This feature seems to be related to a speculative load capability instead..

The server version of the new Intel architecture, code-named Woodcrest, will feature two cores. Intel is also talking about Whitefield, which has as much as twice the L2 cache of Woodcrest and four execution cores.

The company has decided against assigning a codename to this new, common processor microarchitecture, curiously enough. As we’ve noted, the first CPUs based on this design will be available in the second half of 2006 and built using Intel’s 65nm fabrication process.

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