In fact, I think the Core architecture may be even more advantageous in the server/workstation space for various reasons. For one, Woodcrest's true dual-core design with its shared L2 cache presents only a single load on the front-side bus for each chip, while current Paxville and (imminent) Dempsey Xeons require two bus loads per socket. The additional bus loads increase coherency traffic and dictate slower bus clocks. Woodcrest's shared L2 cache, by contrast, may be even more elegant for SMP than AMD's dual-core Opteron design.
There's more, but I should save it for the full article. The next week will be a very busy one, but we should have a lot of good stuff for you soon.