The video source isn’t terribly high res, unfortunately. McGrath describes new features added to Hammer since its launch, but like the slide, he’s a little fuzzy about when various changes have been implemented. Obviously, some of the features haven’t yet arrived, though.
The enhancements include power reductions (gained by using slow but less leaky transistors in non-critical paths) and speed improvements (by using fast but leaky transistors in critical paths). Also, the processor halt and stopclock states have been improved, reducing some unnecessary work previously conducted during these states, resulting in a savings of several hundred milliwatts. Like the Pentium 4, future Hammer chips will feature on-die thermal throttling to cool themselves down if certain temperature limits are reached.
Performance-wise, the big news is the addition of SSE3 instructions, which accelerate a number of different types of computation, including video encoding, scientific computing, and software graphics vertex shaders. (For more on SSE3, see our Prescott review.) Beyond SSE3, the updated Hammer core will convert the LEA instruction, under certain circumstances, into an ADD instruction, which has only a single cycle of latency. AMD’s design mavens have also added additional write-combining buffers to the chip, so it can combine up to four streams of non-cacheable writes, up from two. Hammer’s data prefetch has been improved, as well.
The memory controller has DDR400 support, as we all know, and an improved open page policy.
I believe we’ll see the biggest changes implemented in the upcoming 90nm die shrink of the Hammer core, but like I said, he seems fuzzy on the timing, and some may be available sooner or in current chip revs. (Thanks Stefan Neef, who found out about the presentation via this story at c’t.)
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