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Intel shows off 10-nm Cannon Lake wafer and talks process tech

Wayne Manion Former News Writer Author expertise
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Intel does fine work as a silicon designer, but its manufacturing technology is probably what truly sets the company apart from its competitors. The company held a technology and manufacturing event in Beijing on Monday to show off its latest advances in silicon manufacturing. The most interesting showpiece was a wafer of Cannon Lake silicon built using the company's next-generation 10-nm process technology. The company also talked about its plans to manufacture field-programmable gate arrays (FPGAs) on that process, and announced that it's shipping what it calls the world's first 64-layer 3D NAND for datacenter applications.


Stacy Smith, Intel's group president of manufacturing, poses with a 10-nm Cannon Lake wafer

Intel's senior fellow Mark Bohr reiterated that the company's 10-nm process is an entire generation ahead of the "10-nm" technologies developed by competitors in terms of transistor density and transistor performance, in its view. That's something the company has pointed out loudly in the past. Bohr said Intel's 10-nm tech has the "tightest transistor and metal pitches" and employs the company's "hyper scaling" approach first used in its 14-nm chips. The Cannon Lake wafer on display marked the first occasion that anyone outside of Intel has gotten a chance to see the product.

Intel didn't make any claims about the yields, functionality, or shipping timeline of the chips on its test wafer, however, and there may be a reason for that. Digitimes reported a rumor today that Intel has pushed retail availability of Cannon Lake chips back to the end of 2018. That rumor should be taken with a grain of salt, but if it's true, it would represent the third time Intel has delayed its 10-nm x86 CPUs.

Bohr also talked about his density metric proposal that could make comparisons between different manufacturers' process techs less confusing. The senior fellow noted that Intel continues to work on a low-power process for mobile applications called 22FFL. The company says its latest prototypes can operate at up to 2 GHz with "100x lower leakage" than its previous 22-nm General Purpose (22GP) tech.

Intel also plans to release "Falcon Mesa" FPGAs built on a 10-nm manufacturing technology that should offer reduced power consumption and better meet the demands of the company's datacenter customers. According to the company, these FPGAs build upon Intel's existing Stratix designs. Intel likewise announced that it's started shipping what it says is the first 64-layer 3D TLC NAND SSD suitable for use in datacenter applications. The company hopes that those SSDs will be "broadly available" by the end of 2017.


ARM fellow Gus Yeung displays a 10-nm wafer of Cortex-A75 CPUs

Last but not least, if you'll recall, Intel Custom Foundry announced a partnership with ARM back in August 2016 to accelerate development and implementation of ARM chips on Intel's 10-nm process tech. In Beijing, the silicon manufacturer showed off the first fruits of this partnership, a wafer of 10-nm ARM Cortex-A75 SoCs capable of clock speeds in excess of 3 GHz. The fact that Intel seems to be making its cutting-edge process technology available to fabless semiconductor companies could represent a shake-up to come in the mobile SoC market.

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Wayne Manion Former News Writer

Wayne Manion Former News Writer

Wayne Manion is a tech writer with years of experience in the industry. His key areas of strength include mobile and wireless communications, GPUs, and other computer components, like SSD storage and gaming keyboards.

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