The opportunity doesn’t come along every day to get a detailed peek into the future of computing from the people who are building it. Last week, I had just such a chance. I attended the Common Platform Technology Forum, the annual get-together hosted by IBM, Samsung, and GlobalFoundries. These firms are the members of the Common Platform Alliance, a rather unique consortium of chipmakers.
Co-opetition: IBM, Samsung, and GlobalFoundries together
The Alliance member firms banded together over a decade ago in the face of growing challenges in the quest to achieve ever-higher densities in semiconductor production. Somewhat amazingly, this collaborative partnership has held together over time even though the firms involved sometimes compete directly against one another. The collaborators have seen their share of change, of course, most notably as AMD spun off its manufacturing arm into GlobalFoundries and, not long after that, GloFo acquired fellow Alliance member firm Chartered Semiconductor. However, the remaining entities appear to be as committed to working together as ever, with a clear sense that shared, common interests are at stake.
From left to right: Mike Cadigan (IBM), Dr. Gary Patton (IBM),
Dr. K.H. Kim (Samsung), Mike Noonen (GlobalFoundries)
I’m not aware of anything else quite like the Common Platform Alliance in the tech industry. The members include the #2 and #3 foundries in the world, Samsung and GlobalFoundries, firms that manufacture chips for other companies on contract. (TSMC holds the #1 spot.) Odds are that Samsung manufactured the SoC processor driving the smartphone in your pocket, whether it’s a Galaxy S3 or an iPhone, and if your PC has an AMD processor inside of it, that chip was likely produced by GlobalFoundries. With the rise of mobile devices and the ballooning costs of building chip factories, the foundry business has grown in market share and importance in recent years. Outside of Intel, many of the most prominent names in the chip business, from AMD and Nvidia to Apple and Qualcomm, are “fabless” semiconductor companies that must rely on outside foundries to produce the silicon they design.
IBM’s role in the Alliance is a bit different from the other two firms’. It takes the lead in the research and development of new fabrication techniques, looking ahead a decade or more to determine which avenues might provide the best path to the next reduction in transistor size at near-atomic levels. Much of this research takes place in upstate New York, at the Albany Nanotech Center, where researchers from IBM and academia partner with representatives from the foundries and equipment suppliers to develop upcoming generations of chipmaking tech. GloFo and Samsung then take IBM’s basic process technology, modify it to fit their customers’ needs, and bring it into high-volume production.
If all of that sounds complicated, that’s because it is. This collaborative effort is a mash-up of very large corporations, smaller tools providers, and academics, along with very significant involvement from multiple governments, most notably the State of New York. It is a huge, sprawling enterprise that involves a substantial chunk of the overall semiconductor manufacturing industry. Although Intel typically has been a year or two ahead of the Alliance partners in reaching new, smaller process nodes, the work done by this collaborative effort has contributed in a multitude of ways to the regular drumbeat of Moore’s Law, the founding constant of chipmaking that says the number of transistors jammed into a given space will double roughly every two years. This drumbeat has brought us a precipitous downward trend in the cost of computing, along with steady leaps in performance and reductions in power consumption.
Among other benefits, Moore’s Law has given us affordable, low-power system-on-a-chip (SoC) processors than have enabled the burgeoning markets for smartphones and tablet computers. Although all three Alliance firms have stakes in other markets, most of the talk at the Tech Forum this year was focused on SoCs for mobile applications, the richest trove of potential customers for the foundries. ARM had a conspicuous presence at the Forum, with an emphasis on its partnership with GloFo, while AMD was conspicuous mostly by its absence.
The presentations at the Forum offered glimpses into several stages of upcoming chip technology, from the now-imminent generation beyond today’s 32- and 28-nm silicon to truly wondrous innovations that could be a decade away from making it into real products. The prospects for the continuation of Moore’s Law has been a popular source of concern in recent years, but gloom didn’t dominate the talk at the Forum. What I saw there was both worrying, because of how much hard work remains to be done, and encouraging, given the wealth of resources being thrown at the problems and the astounding potential of technologies now being explored.
What’s next: a new transistor structure at 14 nm
Most immediately, the members of the Common Platform Alliance are working to deliver their next-gen process technologies, whose smallest feature sizes will be 20 and then 14 nm. I should say that each partner is working to deliver its piece of the puzzle, because they tend to diverge when it comes to final implementations. Several years ago, the Alliance articulated a vision of true uniformity and coordination that would allow any product to be manufactured at multiple sites—either at, say, different GloFo fabs in Dresden and New York, or perhaps even at two fabs belonging to different member companies. This year, the Alliance members were frank in admitting that the market instead asked for something else: customization, the ability to tune a solution to a customer’s specific needs. As a result, the sort of strict uniformity that would allow fab-to-fab portability is no longer an important goal for the Alliance.
Below is a slide showing GlobalFoundries’ process tech roadmap for the next little while. Mike Noonen, EVP of Sales, Marketing, Quality and Design at GlobalFoundries, presented this slide during the summit keynote. GloFo was much more forthcoming than Samsung, generally speaking, about its current status and future plans.
As you can see, the road ahead for GlobalFoundries involves a vastly simplified product offering. The firm offers a host of different process types for different market segments in the 28-nm node, but going forward, each step downward in geometry size includes only one process type. GloFo says each process can be tweaked to meet the needs of different types of devices, but the change is still notable. In the past, for instance, AMD Opterons have been fabricated on a super-high-performance process specifically tailored to achieve the high switching speeds needed for multi-gigahertz operation, using techniques like silicon-on-insulator (SOI). GloFo’s 20-nm process, dubbed 20LPM, jettisons SOI in favor of traditional bulk silicon and will serve everything from low-power mobile SoCs to high-performance CPUs. 20LPM is in testing now and is slated to be in production this year.
We are approaching the limits of conventional photolithography, the basis of modern chip fabrication, in which light is directed through a mask and onto a light-sensitive layer of material to etch the patterns that will become circuits. Making the transition to smaller geometries will require some new techniques. Most notably, the 20LPM process employs some double patterning, on the finest metal layers, in order to work around the current resolution limits of photolithography. Double patterning “cheats” by using two different masks, offset slightly, and two light exposures, to achieve a higher effective resolution—a little like interlacing on an old TV screen, only without the resulting flicker.
Since its beginnings, the semiconductor industry has used a mostly flat or “planar” transistor structure that has served it well, but the push to near-atomic-scale devices has led to increases in wasted power, or leakage, that threaten to wipe out the efficiency gains associated with a process shrink. In order to surmount this problem, chipmakers are turning to a transistor structure in which a thin silicon fin protrudes vertically so that it’s surrounded by the gate on three sides, offering more conductive surface area—and thus better efficiency. Intel adopted such a transistor structure, which it calls a “tri-gate transistor,” for its 22-nm process. Most of the rest of the industry, including the Alliance members, calls this sort of structure a FinFET. GlobalFoundries and the Alliance will use conventional planar transistors for their 20-nm process, and then they’ll make the transition to FinFETs at 14 nm.
Although the move to FinFETs is something of a landmark transition, it comes in the form of an incremental step. GloFo’s 14XM process will incorporate elements of 20LPM, building on it rather than supplanting it entirely. Like 20LPM, the 14XM process will include some double-patterning, and it will serve a range of devices from low-power mobile to high-performance computing. GloFo expects 14XM to go into production in the first half of 2014. Right now, the roadmap calls for another new process, 10XM, to come online the very next year, in 2015. The Alliance’s work at 10 nm employs FinFETs and “second-generation” double-patterning.
One thing we don’t know is how GlobalFoundries’ highest-profile customer will take advantage of this new process tech. With the changes in leadership at AMD has come a more conservative approach to both roadmap disclosures and process technology transitions. All we know at present is that the next-generation “Kaveri” APU, successor the Trinity and Richland and competitor to Ivy Bridge, is slated for 28-nm production late in 2013. Several of AMD’s other products, including the low-power “Temash” APU and the “Sea Islands” graphics chips, will be manufactured by TSMC at 28 nm. We’d expect future Opteron and FX processors to make the transition to 20LPM or 14XM at GlobalFoundries, but neither AMD nor GloFo is willing to talk about specifics.
Rather than discussing its cooperation with AMD, GlobalFoundries chose to highlight its partnerships with various important players in the mobile SoC ecosystem. Chief among them is ARM, whose CPU architectures are licensed by the vast majority of SoC makers. GlobalFoundries announced an expanded partnership with ARM in 2012, and at the Forum, it revealed some of the fruits of that collaboration.
Most notably, GloFo used ARM’s Cortex-A9 CPU core as test vehicle for its FinFET-enabled 14XM fab process. Compared to the current super-low-power 28nm process, the Cortex-A9 test chip built on 14XM exhibited considerable improvement, as the slide above illustrates. Those gains can translate into a 62% reduction in power consumption, a 61% increase in operating frequency, or some combination of the two. That’s a very healthy generational improvement, suggesting that the move to FinFETs can keep up the Moore’s Law-style cadence for at least one more generation.
Other GlobalFoundries partners that Noonen highlighted included Cyclos Semiconductor, whose resonant clocking technology was first deployed in AMD’s Piledriver core and contributed to its substantial power savings over the Bulldozer core made on the same process. Cyclos and GloFo are now working together to integrate resonant clocking into the ARM Cortex-A15 at 28 nm, and GlobalFoundries will make this power-saving core available to customers later this year.
Noonen also singled out Adapteva, a small processor startup that has built a simple, dual-issue RISC CPU core with integrated memory and multicore networking, intended to be implemented in massively parallel fashion. GloFo and Adapteva have built a chip at 28 nm that houses 64 CPU cores and achieves a claimed 100 GFLOPS of throughput—at only 2W of power draw and 10 mm² of die space. The two firms have partnered up to market this technology to potential foundry customers, for integration into their SoC solutions.
Partnerships like these obviously move well beyond the traditional contract manufacturing model, and they are a big part of GlobalFoundries’ approach to attracting new customers.
Future process tech—the possibilities and pitfalls
The whole industry is worried, to one degree or another, about whether Moore’s Law can be maintained, along with its attendant cost, power, and speed benefits. At the end of his opening keynote speech at the Forum, IBM vice-president and head of the Semiconductor Research & Development Center, Dr. Garry Patton, said straight up, “I believe CMOS scaling will continue.” Beyond that confident proclamation, though, all sorts of questions remain.
One of the big issues has to do with costs. Although it may be possible to continue pushing to smaller process geometries, doing so is becoming ever more complicated, which means more money must be poured into R&D while manufacturing methods are becoming more elaborate. The resulting higher per-transistor costs may begin to offset the gains won by cramming more transistors into a smaller area. If that effect becomes pronounced, computing could stop becoming cheaper over time at the rate we’ve come to expect. In fact, in a “fireside chat” during the Forum’s afternoon session, Dr. Handel Jones, CEO and owner of consulting firm IBS, said we’re facing this problem even at 20 and 14 nm. He suggested several possible remedies, most notably a renewed emphasis on efficient chip designs that ensure better utilization of the transistors on a die. Jones acknowledged that such efforts could mean chips take longer to design.
Another potential means of improving the economics of chipmaking is the adoption of larger wafers. Right now, state-of-the-art fabs produce chips on round metal wafers that are 300 mm across. The industry has been looking to 450-mm wafers as the next logical step, and Intel recently showed the first fully patterned 450-mm wafer. However, during a Q&A at the Forum, one of the IBM representatives said 450-mm wafers are still some years off, probably arriving near the end of this decade.
Semiconductor scaling faces other hurdles before the end of the decade, too. The Alliance members have articulated a fairly clear path to the 10-nm process node via double-patterning and FinFETs, but beyond that, the road could get bumpy. Dr. Patton told the crowd that moving to 7 nm with conventional lithography would require triple or quadruple patterning, which he characterized as “very expensive.”
Many folks have considered the obvious next step forward for lithography to be the use of shorter-wavelength extreme ultraviolent (EUV) light. IBM appears to be working diligently on developing EUV technology, but Patton threw cold water on the notion that EUV is a foregone conclusion. He explained that the process involves dropping molten tin at a speed of about 150 MPH inside of a tool, zapping it with a laser to broaden it, hitting it with a “real CO₂ laser” to generate plasma, while bouncing off of about six mirrors, each with an efficiency of 6%. Patton called EUV “the biggest change in the history of the industry” and outright disputed the notion that making it feasible is now only a matter of “hard engineering work.” Instead, he said, there are still “real physics problems we have to solve.” As if those words hadn’t raised the uncertainty quotient enough, Dr. Patton then mentioned the possibility that the masks used for EUV lithography could themselves have flaws in them, and he compared finding a 30-nm defect on such a mask to searching over 10% of California’s surface area in order to find a golf ball.
Once the crowd was sufficiently terrified, Patton listed a host of other possibilities for extending semiconductor scaling, some of them involving exotic new materials and techniques. Part of his intent, I think, was to illustrate that the way forward is by no means clear, and that IBM’s research arm is exploring a host of possibilities in hopes of finding the best possible options.
Two of the most intriguing possibilities were further explored by IBM researchers in the afternoon sessions.
|If they do become viable, silicon nanowires may be the last gasp of silicon-based semiconductors.|
Dr. Mukesh Khare, Director of the Semiconductor Alliance at IBM, outlined his group’s research into silicon nanowires. Nanowires are long, thin silicon structures between about three and 20 nm in diameter. These wires could serve as the building block for transistors in the future. In fact, the basic transistor structure doesn’t look too terribly different from the FinFETs of today; the nanowire takes the place currently occupied by a silicon fin. Nanowires are created by etching a long and relatively thick bar of silicon using conventional lithography and then using hydrogen to anneal the silicon. The annealing process leaves behind a thinner, rounder silicon “wire” structure that is suspended above the substrate layer below it. After that, gate material is deposited all around the nanowire, even beneath it, for even better exposure of surface area than a FinFET’s triple-sided contact area. There are still hurdles to overcome in making nanowires a viable manufacturing technology, but the potential is undeniable, especially since one can easily imagine how nanowire creation could be integrated into current manufacturing methods.
If they do become viable, silicon nanowires may be the last gasp of silicon-based semiconductors. According to Dr. Supratik Guha, Director of the Physical Sciences Department at IBM Research, silicon ceases to be a good material “when you come to atomic dimensions.” Seven nanometers is about as small as silicon can go; beyond that point, other materials might be superior. For the past couple of years, his group at IBM Research has been exploring the most promising alternative material: carbon—specifically, the rolled lattice structures known as carbon nanotubes.
Since their discovery, carbon nanotubes have been the subject of intensive study, in part because they can act as semiconductors. You can imagine these tiny tubes, typically about one nanometer in diameter, taking the place of a fin or nanowire in a transistor layout. Dr. Guha explained that the first carbon nanotube transistors were created around 2001, and some time later, researchers figured out how to encase a tube with gate material. In 2007, the first carbon nanotube circuit was demonstrated.
Part of the appeal here is that, as Guha put it, the “short-channel characteristics for carbon nanotubes are very, very good.” To put it simply, that means carbon nanotube-based chips could in theory have relatively low power leakage, and leakage is the #1 problem to be managed in today’s silicon chips. Guha said IBM did a simulation of a hypothetical carbon nanotube-based chip, comparing it to FinFET silicon at nodes as small as 5 nm, with promising results. At the same power density, carbon nanotubes could offer three times the performance of silicon FinFETs—or at equivalent performance, they could require one-third the power.
Although carbon nanotubes hold promise, incorporating them successfully into some variant of today’s chip manufacturing methods will be no small feat. Carbon nanotubes are “grown” in a lab using a chemical process, and they exit that process with impurities—some portion of the resulting nanotubes are metallic conductors. The metallic nanotubes must be culled from the rest, so that a pure batch of semiconducting nanotubes remains. The goal then is to deposit the nanotubes in a layer atop a traditional silicon wafer and then, somehow, to align them into a precise, regular layout, so the wafer can be patterned using lithography.
Amazingly, researchers have made tremendous progress with each of these challenges. Dr. Guha said the IBM team can now sort nanotubes well enough to achieve 99.9% purity using an automated, parallel, electrical sorting method. There’s still work to be done to achieve the “four or five nines” of purity needed for production, but Guha believes the purity challenge will be solved.
The next challenge seems even more daunting: somehow, to arrange the nanotubes in a regular, predictable fashion on top of a silicon wafer. The answer IBM researchers are pursuing uses a bit of dark magic known as directed self-assembly (DSA), in which nano-scale materials are coaxed into forming ordered structures. Already, Guha reported, they are able to align about 10 nanotubes per micron with consistency. That ability has led to another breakthrough: the chip-scale fabrication of positioned carbon nanotube-based devices. Last year, IBM researchers demonstrated a chip with 10,000 carbon nanotube devices onboard, produced using techniques similar to silicon processing. As I mentioned above, IBM has developed a process for encasing carbon nanotubes with gate materials, much as they do with silicon nanowires. The result is an all-around carbon nanotube FET in which the gate contact is self-aligned properly to the source and drain.
So yes, researchers are making considerable progress toward using carbon nanotubes in chips. What they have now, though, is only a beginning. The test chips give them the ability to run statistical analysis, so the difficult work of increasing alignment precision and reducing defects can commence. Dr. Guha expects to see contributions from multiple disciplines coming into the effort, helping to sort out problems of chemistry, the physics of quantized systems, and the behavior of materials at atomic scales. He expressed confidence that the Common Platform team “has the horsepower to make it happen.” If the effort succeeds, we could see workable carbon nanotube-based chip fabrication technology somewhere in the 2019-2022 time frame.
Ultimately, Patton envisions chips with multiple layers stacked on top of one another in 3D: a photonics plane, a memory plane, and a logic plane. A chip built in this fashion, he said, could have 300 cores, 30GB of embedded DRAM, and “incredible bandwidth” to tie it all together. One gets the impression that he intends to help make it happen.
If that isn’t an antidote to the gloom coming from some quarters, I don’t know what is.