Since Rory Read took the helm at AMD, he and his management team have crafted and pursued a new strategy for the company’s future. Somewhat unusually for a major CPU maker, the “new” AMD has been pretty reserved about communicating its plans. In fact, I think the only truly important revelations from the new AMD have come in the context of just two events, an Analyst Day in 2012 and a “Core Innovation Update” this morning.
Fortunately, after this morning, we know a whole heck of a lot more about AMD’s strategy going forward, about what Read’s “ambidextrous” approach to development means, and about specific products coming in the next two years. We now know that AMD intends to compete where it has done well historically—in desktops, servers, and laptops, as well as embedded systems and mobile devices—by fielding CPUs compatible with the two major instruction set architectures: ARM and x86.
The biggest news is about chips coming in 2016, but let’s step through these things in order, since they’re all part of a progression.
The first bit of news worth noting today was a live demo of AMD’s Seattle chip. This system-on-a-chip is intended for use in servers, and it incorporates eight ARM Cortex-A57 CPU cores. AMD demoed this SoC running Linux and the LAMP web services stack, and the firm said it intends for the 28-nm Seattle to ship in volume by the end of this year.
AMD’s presence lends instant credibility to the nascent ARM server market. The pull from big consumers of server-class hardware like Google and Facebook has already set the stage for ARM CPUs to succeed here, but the hardware options for 64-bit ARM processors have so far been limited.
AMD has also been shipping server versions of consumer APUs like Kabini, so it has low-power, server-class SoCs for both ARM and x86 in its quiver for 2014.
What happens in 2015 is even more interesting. AMD has updated SoCs in the works based on a 20-nm fabrication process, and those chips will adopt a common “design framework,” in the words of Dr. Lisa Su, that goes by the code-name “SkyBridge.” The idea with SkyBridge is for ARM and x86 versions of AMD’s products to share infrastructure, so they’ll be pin-compatible with the same motherboards and systems, regardless of which ISA they can execute.
Dr. Su said she expects the first example of SkyBridge products to target embedded systems and “some client markets,” presumably low-power devices like tablets or small laptops. These products will use either the “Puma+” CPU cores that AMD just shipped in its Mullins APU or a low-power-optimized version of the Cortex-A57 core licensed from ARM. One can imagine a tablet based on this first low-power SkyBridge platform that could ship with an ARM-compatible SoC for Android and another variant, equipped with the x86-compatible chip instead, running Windows. The hardware could be identical save for the SoC itself.
Both of these chips will incorporate key AMD technologies, including the GCN graphics architecture that powers all current Radeon GPUs and support for HSA, AMD’s model for shared execution of code across CPU and GPU cores in the same system. HSA provides a layer of abstraction above the execution hardware, so making use of it on both x86 and ARM ought to prove reasonably seamless. True HSA support in hardware requires a coherent path to memory for the GPU, like AMD built into Kaveri, so its inclusion in an ARM-based SoC will require some honest work.
According to Su, some of these SkyBridge processors and motherboards could have a socket-based infrastructure, probably much like what’s out there now for desktop Kabini. That development could give ARM an opportunity to make inroads on the desktop, particularly in emerging markets where the current desktop Kabini may already be getting some traction.
SkyBridge will start with these low-power SoCs, but Dr. Su made clear that this dual-track development framework will eventually encompass a whole family of products across different markets. We’ll likely see different pinouts and sockets for chips of different sizes, with an ARM and x86 version of the silicon in each case.
SkyBridge sets the stage for new products coming in 2016, and that’s where things truly become intriguing.
AMD revealed that it is working on not one, but two brand-new, built-from-scratch CPU architectures. It has licensed the ARMv8 ISA and, in Dr. Su’s words, “we are already well on our way to developing custom ARM cores.” At the same time, AMD is building a brand-new, x86-compatible CPU core that will serve to replace Bulldozer and its lineage.
I’m not quite sure whether the biggest news here is the announcement of a new high-end x86 architecture from AMD or the fact that ARMv8 is getting the same treatment.
Since we’re talking about a replacement for Bulldozer, this is an entirely different class of beast from the “Puma+” and Cortex-A57 cores in the first SkyBridge parts. AMD’s execs noted that these are high-frequency, high-performance CPU cores that will span the range from laptops to desktops to servers—and not just “microservers.” We don’t know exactly how big they’ll be compared to Bulldozer or, say, Haswell. The smartest play might be to aim for something a little smaller than those cores, but that’s the basic class of performance they’re undoubtedly meant to achieve. AMD is returning to its roots, aiming to produce a best-in-class big core.
Well, two of them, this time.
AMD used the code-name “K12” to refer to the ARM core. I’m not clear yet whether that name also applies to the x86 core.
These two CPU microarchitectures will be, in the words of CTO Mark Papermaster, “sister cores.” (Papermaster came to AMD from Apple, and he managed to lure CPU architect Jim Keller from Apple, too, shortly after Keller led the development of Apple’s own 64-bit ARM core.) Keller explained during this morning’s Q&A session that the new cores will share more than just pin compatibility. He said they will be “compatible at the pin level and inside.” That likely means that the ARM and x86 SoCs based on these new cores will share the same internal plumbing—things like the I/O ring around the edges of the chip and the last-level cache. AMD’s design teams will then be able to fit, say, four ARM cores or four x86 cores into the space on the interior section of the chip.
Presumably, these sister x86 and ARM cores will perform about the same, but they evidently are not just two variants of the same microarchitecture adapted to different ISAs. Keller was very complimentary about the ARMv8 ISA in his talk, saying it has more registers and “a proper three-operand instruction set.” He noted that ARMv8 doesn’t require the same instruction decoding hardware as an x86 processor, leaving more room to concentrate on performance. Keller even outright said that “the way we built ARM is a little different from x86” because it “has a bigger engine.” I take that to mean AMD’s ARM-compatible microarchitecture is somewhat wider than its sister, x86-compatible core. We’ll have to see how that difference translates into performance in the long run.
Deep into the Q&A, some analysts were asking how AMD would differentiate itself from other contenders in the burgeoning ARM server space. Given what Keller and Papermaster shared, the answer seems quite obvious. If AMD were only offering A57-based parts like Seattle, it might have trouble standing out, but we’re talking now about a full-fledged, next-generation processor worthy of the Opteron name. The other players in the ARM server space have, at least so far, concentrated almost exclusively on small, lower-power cores. Few have even made the transition to 64-bit addressing, and nothing in ARM’s own portfolio of licensed cores is anywhere near this potent. The ARM-compatible K12 may be one of a kind if it arrives on schedule in 2016.
If it enables the folks building data centers to get the same sort of per-thread performance from ARM-based servers that they can from x86 processors, the K12 could obviate the need for x86 CPUs almost entirely. It could help key a dramatic transition from a single dominant ISA to two competing options—or it might even spark a longer transition away from the Intel-dominated x86 world to one ruled by the more open and expansive ARM ecosystem.
With this “ambidextrous” plan, AMD can win regardless of how the ISA battle plays out. That concept sounded promising when Rory Read first floated it a couple of years ago, but now that we can see more details, it seems even better than most of us probably expected.
As always, everything depends on the specifics. AMD has to deliver these products, and they have to perform well in order to matter. This company can’t afford another Bulldozer-style fiasco. But in some senses, AMD now looks to be even better positioned than Intel for the next few years. We haven’t been able to say that for a long, long time.