Intel hasn't taken too kindly to the revolution in mobile devices that has happened largely without its participation. The rise of smartphones and tablets with ARM-compatible chips onboard has become a major threat to Intel's dominance in the processor business—and this is, after all, a company built on the mantra that "only the paranoid survive."
Thus, for several technology generations, Intel has slowly adjusted its heading to better compete in mobile devices. The firm has used its expertise in chip manufacturing and design to cram PC-like performance into ever smaller footprints. Last year's Haswell chip brought huge progress in terms of power consumption, battery life, and system sizes. This year, a new processor code-named Broadwell promises dramatic gains once again, thanks in part to the world-class nanoscale technology in Intel's 14-nm chip fabrication process.
The first Broadwell-based processors will carry a new brand name, Core M, and they will target very small systems indeed: iPad-like tablets that are less than nine millimeters thick and have no fans to cool them. Fitting a PC-class processor into such a device is no easy task. Intel claims to have achieved this feat by tweaking nearly every part of the Broadwell silicon and surrounding platform in order to reduce its size and power consumption. More impressively, they say they've kept performance steady at the same time.
Enforcing Moore's Law: Intel's 14-nm process
One key ingredient in Broadwell's success is Intel's 14-nm manufacturing process, the world's first of its kind. Broadwell has been very publicly delayed due to some teething problems with this new process. In a briefing last week, however, Intel VP and Director of 14-nm Technology Development Sanjay Natarajan told us that the 14-nm process is now qualified and in volume production.
In fact, Natarajan shared quite a few specifics about the 14-nm process in order to underscore Intel's success. His core message: the 14-nm process provides true scaling from the prior 22-nm node, with virtually all of the traditional benefits of Moore's Law intact.
Moore's Law has made the massive advances in microelectronics over the past 40 years possible. Its basic formulation says that the number of transistors one can pack into a given area of a chip will roughly double every couple of years. Intel has moved mountains to keep Moore's Law on track, and it has reaped huge benefits for doing so. The rest of the semiconductor industry has followed the same path, but in recent years, it has done so from a fair distance behind Intel. For instance, this 14-nm process is the second generation to employ what Intel calls tri-gate transistors (which the rest of the industry calls FinFETs). Other firms have yet to ship first-generation FinFET silicon.
Shrinking on-chip features to ever-smaller dimensions is an incredibly difficult problem, and the complexity of the task has grown with each successive generation. When questioned during a press briefing we attended, Natarajan was quick to admit that the familiar naming convention we use to denote manufacturing processes is mostly just branding. The size of various on-chip elements diverged from the process name years ago, perhaps around the 90-nm node. That said, Intel Fellow and process development guru Mark Bohr quickly pointed out that transistor densities have continued to scale as expected from one generation to the next. In other words, Moore's Law is alive and well.
To illustrate, Natarajan showed how the fins comprising Intel's tri-grate transistors have grown closer together at the 14-nm node—fin pitch has been reduced from 60 to 42 nm—while the fins themselves have grown taller and thinner. The closer placement improves density, while the new fin structure allows for increased drive current and thus better performance. This higher performance, in turn, allows Intel to use fewer fins for some on-chip structures, further increasing the effective density of the process. Fewer fins also means lower capacitance and more power-efficient operation.
The gate pitch has been reduced from 90 to 70 nm and, as shown above, the spacing of the smallest interconnects has dropped even more dramatically, from 80 to 52 nm.
The cumulative result of these changes is perhaps best demonstrated by looking at a fairly common benchmark: the size of a six-transistor SRAM cell. On Intel's 22-nm process, a 6T cell occupies 0.108 square micrometers of space. The same structure at 14-nm takes up only 0.0588 square micrometers—or 54% of the area required at 22-nm. That's classic Moore's Law-style area scaling.
The benefits of the 14-nm process extend beyond sheer density. Natarajan shared the graph above to convey the power and performance advances offered by this 14-nm process. Essentially, it can flip bits at higher speeds than prior generations while losing less power in the form of leakage along the way. Intel can choose to tune its products for different points along the leakage-performance curve shown above, but in each case, chips built on the 14-nm process should offer a nicer set of tradeoffs than those from prior process generations.
This next illustration is perhaps the most telling, because it addresses one of the key threats to Moore's Law going forward: economics. I said before that the transition to each smaller process node has been more difficult than the last. Chipmakers have had to use ever more exotic techniques like double-patterning—creating two separate masks for photolithography and exposing them at a slight offset—in order to achieve higher densities. Doing so increases costs, and as a result, one of the key corollaries of Moore's Law has been threatened. If moving to finer process nodes can't reduce the cost per transistor, the march of ever-more-complex microelectronics could slow down considerably. Some chipmakers have hinted that we'll be approaching that point very soon.
By contrast, Intel says the math continues to work well for its process tech. The area per transistor is dropping steadily over time, while the cost for each square millimeter of silicon is rising at a slower pace. The net result remains a steady decrease in cost per transistor through the 14-nm node. In fact, Bohr told us that he expects Intel to deliver an even lower cost per transistor in its upcoming 10-nm process.
Despite the delays, then, Intel is bullish about its process tech advancements and confident that its 14-nm technology is ready to roll. Natarajan says the company is now shipping 14-nm production chips to its customers, and the first Core M-based products should arrive on store shelves in time for this year's holiday season. Two fabs, one in Oregon and the other in Arizona, are slated to be producing 14-nm wafers this year, with another plant in Ireland scheduled to ramp up production in 2015. Natarajan expects sufficient 14-nm silicon yields and wafer volumes to support "multiple 14-nm product ramps in the first half of 2015."