GCN goes low-power
AMD has done some power optimization on the GPU side of things, as well. Again, the changes were all intended to help tailor Carrizo for its intended power envelope. The team tuned Carrizo's GPU cores for low-power operation by reducing their reliance on high-performance devices that bleed more power in the form of leakage. By selecting cooler, lower-power options from the suite of devices available in the 28-nm process, they were able to realize substantial efficiency gains: either a 20% power savings at the same clock speed or a 10% higher operating frequency in the same power budget.
These optimizations allowed AMD to enable all eight of the GCN compute units simultaneously in the low-power version of Carrizo. Previously, in the low-power Kaveri, they had to limit the chip to six CUs at once in order to avoid exceeding the APU's power budget.
Again, optimizing an integrated GPU in this fashion involves a trade-off. The peak operating frequencies of the graphics cores in Carrizo are likely lower than Kaveri's, which would translate into lower peak performance at higher power levels.
Chips need a certain minimum amount of voltage in order to operate properly without crashing. Unfortunately, the voltage supplied to a chip in a typical system isn't always perfectly steady. To avoid problems, chipmakers typically supply a little extra voltage to their chips. Naffziger told us AMD has generally overvolted by about 10% in order to compensate for potential voltage droop. That may not sound like much, but a chip's power draw is determined in large part by the square of the voltage, so keeping voltage low is a critical goal.
AMD has an innovative solution to this problem: voltage-adaptive operation. The firm's CPU cores have the ability to track the supplied voltage in real time, at "sub-nanosecond" speeds, in order to detect when voltage droops. The chip can then reduce its operating speed briefly in response to the voltage reduction, preventing a crash.
Naffziger notes that voltage droop happens "less than one percent of the time," so voltage-adaptive operation should have no noticeable impact on performance. Instead, he says, "we just get a bunch of that power waste back" by not needing to overvolt the silicon to ensure stability. The firm can choose to turn the power savings into higher clock speeds, too, if it wishes.
Voltage-adaptive operation was built into Kaveri's CPU cores, but in Carrizo, it's been incorporated into the graphics CUs, as well. AMD estimates this technique reduces power consumption by up to 19% for its CPU cores and by as much as 10% for its integrated graphics.
Adaptive voltage and frequency scaling
AMD has also sought to reduce voltage in Carrizo by giving the chip the ability to tune itself. More precisely, this optimization, known as Adaptive Voltage and Frequency Scaling (AVFS) currently applies only to the Excavator CPU cores.
Each Excavator core includes a scattered collection of AVFS "modules" that include replica versions of critical logic pathways in the CPU. The AVFS modules can test these pathways for stability at different voltage levels in real time as the chip operates. AVFS thus allows the CPU core to know its lowest safe operating voltage for the present conditions, including the clock speed and temperature.
AMD estimates that the voltage reductions made possible by AVFS can cut power consumption between five and 15% at a given clock speed. As with many of the other optimizations in Carrizo, the biggest gains from AVFS come at lower power levels.
For several generations, AMD's mobile platforms have been missing support for a Windows 8 feature known as Connected Standby mode. This is the mode that allows Windows-based systems to mimic the behavior of phones and tablets by dropping into a deep sleep state that uses very little power. The system can then wake up briefly to check for any incoming messages and notify the user, or it can simply awaken very quickly when the user is ready to resume working.
AMD didn't talk about Connected Standby in its Carrizo presentation, but it did confirm that the chip will support the primary power state needed for this feature, a state known as S0i3. In this state, the power management subsystem gates off power to nearly all of the APU's silicon, reducing chip-wide power consumption to less than 50 milliwatts. The time required to enter and exit S0i3 mode is much lower than the time needed to transition to the traditional S3 standby mode. AMD says the APU can drop into S0i3 in less than a second.
This addition doesn't yet give AMD's big APU all of the aggressive "active idle" capabilities that Intel built into its mobile Haswell offerings, in part because Carrizo lacks the fast state transitions made possible by Haswell's integrated voltage regulation. Intel has said that Haswell can wake from being completely powered down in under three milliseconds. Still, the addition of S0i3 to Carrizo is a step in the right direction.
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