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The future is still fusion?
Back in 2012, AMD's then-new CTO Mark Papermaster laid out a development direction for AMD that involved SoC-style design principles. Most mobile SoCs are built using a particular approach where discrete functional blocks are glued together using a common interconnect, like ARM's AMBA spec. This approach, combining modularity with a common interconnect, can allow for rapid development of new chips, with shorter design cycles and more flexibility. Since Papermaster joined AMD, the firm has put together a pretty good track record of delivering new APUs on a fairly regular basis, but it hasn't yet produced a big x86 APU based on SoC-style design principles.

For example, for most intents and purposes, AMD's Kaveri is kind of a Radeon glued to a Bulldozer core. Rather than sharing a memory controller over an interconnect fabric that maintains memory coherency—as one would expect with the SoC approach—Kaveri's GPU has three paths to memory: a 512-bit Radeon memory bus, a 256-bit "Fusion Compute Link" into CPU-owned memory, and another 256-bit link into CPU-owned memory that maintains coherency. In theory, with a proper coherent fabric, these three links could be merged into one, saving power, reducing complexity, and quite probably improving performance. The use of a proper interconnect fabric would also allow AMD to swap in newer or larger graphics IP without requiring as much customization.

AMD surely chose to build Kaveri as it did for good reasons, most notably because it needed to deliver a product to the market in a certain time frame. Still, one can't help but note that Intel's original Sandy Bridge chip had a common ring interconnect joining together the CPU cores, graphics, shared last-level cache, and I/O. From a certain perspective, although it wasn't meant for this mission, Sandy Bridge's basic architecture was arguably a better fit for AMD's HSA execution model than Kaveri.

We don't yet know all of the details about AMD's new APU, but the firm confirmed that Carrizo follows the same basic implementation style as Kaveri. Carrizo doesn't yet embrace the SoC-style design methodology AMD intends to adopt.

That said, AMD's new APU doesn't have to follow this approach in order to be a great product for 15W laptops. I'm persuaded AMD's power-optimizations efforts are a smart choice for this generation. Given that it takes about four years to build a chip of this class from scratch, I would expect next year's models finally to make the transition to a more modular layout.

Zen and the art of feature matrices
Speaking of the future, one of the most interesting slides AMD had to share with us was the following matrix of product features, including some features that are coming in future products. Have a look, since it offers a few juicy tidbits of new information.

I'm not really clear on how all of these time frames map to products, exactly, but AMD told me the features included in Carrizo count as "in product" options in the blue boxes. Some of these things we already know about, such as AVFS and voltage-adaptive operation. Others are still mysterious, like inter-frame power gating, which could be a GPU-focused optimization. (Hmm!) I suspect we'll know more about these technologies once Carrizo hits the market mid-year.

The "in development" features in purple are probably giving us some of our first insights into the chips based on AMD's upcoming Zen microarchitecture. Most notable among them is integrated voltage regulation, a la Intel's Haswell and Broadwell CPUs. Some of the other features listed look to be power-management capabilities made possible by the faster switching and finer granularity of integrated voltage regulation. For instance, per-IP adaptive voltage likely means separate supply rails for various on-chip units. Environment and reliability-aware boost could be an extension of AVFS. The workload-aware energy optimization sounds a lot like the Energy Efficient Turbo feature Intel built into its Haswell-EP processors; this feature monitors stalls on the CPU and reduces clock speeds if the CPU core's performance is limited by external factors.

I suspect "advanced bandwidth compression" is a GPU feature. AMD introduced much-improved frame buffer compression in its Tonga GPU last fall. Looks like that capability could make it into APU silicon in 2016 alongside Zen. I hate to steal the spotlight from Carrizo, but Zen could be where AMD really catches up to Intel in a big way.

A big win for efficiency in laptops
We don't have much in the way of specifics about the full extent of Carrizo's power efficiency gains over the prior generation just yet, but AMD is claiming "double digit" increases in both performance and battery life.

The power efficiency plot above helps tell that tale visually. We'll probably have to wait until closer to Carrizo's release before we have more specific numbers. Regardless, this power-efficiency progress is all part of AMD's goal, stated last year, to make its products 25 times more power-efficient by the year 2020.

AMD tells us Carrizo parts will fit into power envelopes ranging from 12 to 35W. That is the "breadth of the design space" for this chip, although, cryptically, the firm also says that "doesn't mean it doesn't scale beyond that." I'm not sure what to make of that statement. Either it's purely an engineering sentiment, or it might mean we could eventually see Carrizo-based products that push below 12W or above 35W, though presumably they wouldn't be entirely optimal implementations of the chip.

Whatever the case, AMD has pretty clearly aimed for a specific target with this generation of its APU technology. In Naffziger's words, "We optimized for a range and knocked it out of the park." The result may be a chip that competes credibly against Intel's 14-nm mobile Broadwell offerings. If AMD can manage that feat with 28-nm silicon, it will be quite an achievement, given everything.TR

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