At its Technology and Manufacturing Day event in San Francisco this week, Intel delivered a stern rebuke to the growing chorus of questioners asking whether it’s lost its process-technology lead. The company brought several luminaries from its manufacturing division on stage to talk about how its 14-nm process technology compares to its competitors’ 16-nm, 14-nm, and 10-nm offerings. It also offered some projections about how its upcoming 10-nm process will stack up.
From the top, Intel came right out and said what many in the industry have understood for some time: that the names of recent process nodes have become unmoored from the actual characteristics of the underlying technologies they claim to represent. A brief refresher: Intel’s cutting-edge Broadwell, Skylake, and Kaby Lake CPUs are all manufactured on its proprietary 14-nm FinFET process. AMD’s Ryzen CPUs and Polaris GPUs are produced on GlobalFoundries’ 14-nm FinFET technology, and Nvidia fabricates many of its Pascal GPUs on TSMC’s 16-nm FinFET tech. If one were to take those numbers at face value, one might believe that Intel, TSMC, and GlobalFoundries are all on relatively even footing when it comes to process tech.
The worry among investors and the analyst community, in turn, seems to be that Intel’s competitors will beat it to the next process node advance. For just one example of this perceived threat, Qualcomm’s upcoming Snapdragon 835 chip will be fabricated on Samsung’s 10-nm process, and that chip (plus Samsung’s Exynos 8895 SoC) will both be shipping soon in Samsung’s Galaxy S8. MediaTek has previously announced plans to make its Helio X30 SoC on TSMC’s 10-nm process, as well. That SoC could arrive sometime this year.
Not so fast, Intel says. The company points out that pitch measurements are just one characteristic of a semiconductor product, and it feels that using these measurements alone to characterize process capabilities isn’t painting a complete picture.
Instead, the company argues that a more useful measure of process advancement is to consider the density of logic transistors that a given process can achieve, independent of its node. With modern process technologies, the company suggests that measuring logic density using megatransistors per square millimeter (henceforth MTr/mm²) offers a better picture of what a given process can do.
Intel Senior Fellow Mark Bohr says the company is modeling this metric using a theoretical logic block comprising 60% NAND gates (not to be confused with an NAND flash cell) as a simple structure and 40% scan flip-flops to represent more complex structures.
The company introduced this metric using its 14-nm FinFET process as an example. That process can achieve 37.5 MTr/mm², compared to 29 MTr/mm² in what is presumably TSMC’s 16-nm process and 30.5 MTr/mm² in GlobalFoundries’ 14-nm FinFET technology. Intel says that at worst, its 14-nm process is still 25% denser than what its competitors can achieve, something that traditional n-nm feature sizes alone don’t capture.
Intel extended this measure to account for its guesses at how its competitors’ 10-nm-class products will stack up by this transistor-density measure, since the company openly admits that it hasn’t had the opportunity to reverse-engineer any shipping 10-nm products yet. Still, the blue team estimates its competitors’ 10-nm processes will offer only slightly higher logic density than its own 14-nm FinFET process—three years after chips fabricated on that tech began shipping.
The point of all this horn-tooting is that Intel believes its 14-nm process has plenty of life left in it. As we first saw with its Kaby Lake CPUs, Intel isn’t producing just two generations of chips on a given process node any longer. As part of the company’s “process-architecture-optimize” product strategy, Kaby chips are fabricated on what Intel calls a “14nm+” process, and it intends to perform another round of optimizations to produce a “14nm++” version of that process.
14nm++ is claimed to offer 25% greater performance at a given power level than the unoptimized 14nm process first used to produce Broadwell and Skylake chips, or as much as 52% less power consumption for the same level of performance. In fact, Intel’s projections show that the transistor performance of 14nm++ will actually exceed that of its first generation of 10-nm products. Expect to see 14nm++ underpin Intel’s rumored Coffee Lake CPUs later this year.
Popping the hood on Intel’s 10-nm process
Intel being Intel, the company also offered a full-throated defense of its advancements versus the unflinching curve of Moore’s Law, which until recently was defined as a doubling of transistor density within a given area every two years.
The company says that while its node transitions have been taking place over longer periods of time these days, it’s also been exceeding that 2x density improvement over those periods using an armory of innovations that you’ll now hear referred to as “hyper-scaling.” That marketing-friendly catch-all refers to fabrication techniques the company began using at 14nm to achieve higher density, including a proprietary technology it calls self-aligned double patterning. On average, Intel says its “hyper-scaling” achievements allow it to keep up with the density increases that Moore’s Law would dictate, even if they’re not happening on a strict two-year cadence.
Back to those “hyper-scaling” techniques, though. Multi-patterning in general is just one way foundries are overcoming the challenges of laying down chips at the extremely small feature sizes of today’s process technologies, but Intel thinks its self-aligned techniques offer greater control and a higher-quality end result compared to what it describes as its competitors’ multiple-stage lithography-etch processes. Intel claims that the self-aligning multiple-patterning process it uses allows it to lay down features predictably, resulting in high-quality circuit elements and predictable performance in the end product.
In contrast, Intel thinks the multi-stage litho-etch process used by its competitors for multi-patterning can only be as good as the precision of the masking laid down before each etching step, and it claims that process is prone to imprecision, resulting in lower-quality features and less consistent electrical characteristics in the final chip.
More broadly, Intel is defining its “hyper-scaling” innovations as proprietary technology that will allow it to achieve greater density increases than a pure process shrink alone would. As it moves to 10-nm production, Intel says it’ll be using three of these techniques to achieve those “hyper-scaling” gains.
For one, Intel 10-nm FinFET will increase fin height and decrease fin pitch, two improvements that are the hallmarks of higher-performance 3D transistors. 10-nm fin pitch will decrease from 42 nm on the 14-nm process to 34 nm on 10nm, while fin height will grow from 42 nm to 54 nm. To lay down those fins, 10nm will use an industry-standard 193-nm light source paired with another advance in Intel’s multi-patterning technology, called self-aligned quad-patterning.
Additionally, this method will allow Intel to achieve a 36-nm interconnect pitch, which it claims is the tightest in the industry.
The logic cell height of Intel 10-nm will also be shrinking compared to 14-nm technologies. A basic logic cell in Intel 14-nm is 399nm tall, while 10-nm will decrease that figure to 272 nm, or a 0.68x reduction.
Aside from the changes in feature sizes, Intel will also be using two new techniques to reduce the area occupied by each logic cell on the chip. The first of these is called contact-over-active-gate technology. In the past, Intel says contacts have had to be laid down beside a transistor. Contact-over-active-gate allows Intel to place these elements directly above the transistor, saving space and increasing density. Intel says the contact-over-active-gate approach allows it to achieve 10% greater logic density in a given area than it would without the tech.
Another change in Intel’s move to 10nm is the use of single dummy gates at the edges of its logic cells. Dummy gates are used to isolate logic devices from one another on the chip, and Intel’s 14-nm node used two of these features at each edge of each logic cell. Reducing the number of dummy gates per cell from two to one lets the company enjoy 20% greater area scaling compared to its approach at 14nm.
All together, Intel claims the four improvements it’s disclosing for its 10-nm process let it achieve a 0.37x reduction in logic area on die compared to its 14-nm process, as well as a 2.7x logic density improvement—well above the 2x scaling that Moore’s Law would lead us to expect.
Taken as a whole, a hypothetical Intel chip with logic, I/O, and SRAM circuitry is purported to be 0.43x the size of a similar chip fabricated on Intel 14-nm FinFET.
Using the MTr/mm² metric it introduced yesterday, Intel claims its 10-nm process will deliver an eye-popping 100 MTr/mm² for logic, and it believes its competitors’ 10-nm processes will deliver roughly half that density. In remarkably pointed commentary, Intel says that density deficit represents a three-year lead for its own process technology.
Over the life of the 10-nm process, Intel further plans to deliver two refinements to the node that will improve performance, just as it will for its 14-nm tech. For its first round of refinements, the company expects 15% better performance at the same power level, or similar performance for 30% less power.
As we noted earlier, however, the company doesn’t expect its 10-nm transistors to meet or exceed the performance of its third-gen 14-nm FinFETs until this first round of refinements, or perhaps even until the second round of refinements. The advantages from 10nm could primarily come from the increase in density and a decrease in power consumption, at least at first.
The future of Moore’s Law
Taken together, the better-than-Moore’s-Law density improvements Intel claims from its “hyper-scaling” techniques seem to point to another redefining of Moore’s Law. Instead of considering its improvements using a rigid two-year cadence, the company suggests that the longer intervals between process nodes combined with the greater-than-2x-improvement in logic density per node should be viewed as averaging out to the expected improvement over time.
Fair enough, I suppose, presuming that Intel’s future move to a seven-nanometer process can happen quickly enough and the scaling benefits such a move provides are great enough that the “hyper-scaling” trend continues to hold. In any case, the details Intel has shared about its 10-nm process have me excited for the potential of chips produced on that node. Furthermore, if the company’s new MTr/mm² metric is accurate, the company will simply be able to pack far more transistors into a given logic area than its competitors’ 10-nm-class processes will.
That said, Intel doesn’t seem to be ready to introduce any 10-nm products any time before sometime in 2018 at the earliest. That release window coincides with TSMC’s plans to begin producing 7-nm-class products, which could be more competitive on the density metric that Intel is touting. Without setting up electron microscopes and some kind of X-ray tomography system in the TR labs, we can’t verify any of these claims independently, but we look forward to the performance and power-saving advancements these new production techniques herald when they do finally yield production silicon.