Popping the hood on Intel's 10-nm process
Intel being Intel, the company also offered a full-throated defense of its advancements versus the unflinching curve of Moore's Law, which until recently was defined as a doubling of transistor density within a given area every two years.
The company says that while its node transitions have been taking place over longer periods of time these days, it's also been exceeding that 2x density improvement over those periods using an armory of innovations that you'll now hear referred to as "hyper-scaling." That marketing-friendly catch-all refers to fabrication techniques the company began using at 14nm to achieve higher density, including a proprietary technology it calls self-aligned double patterning. On average, Intel says its "hyper-scaling" achievements allow it to keep up with the density increases that Moore's Law would dictate, even if they're not happening on a strict two-year cadence.
Back to those "hyper-scaling" techniques, though. Multi-patterning in general is just one way foundries are overcoming the challenges of laying down chips at the extremely small feature sizes of today's process technologies, but Intel thinks its self-aligned techniques offer greater control and a higher-quality end result compared to what it describes as its competitors' multiple-stage lithography-etch processes. Intel claims that the self-aligning multiple-patterning process it uses allows it to lay down features predictably, resulting in high-quality circuit elements and predictable performance in the end product.
In contrast, Intel thinks the multi-stage litho-etch process used by its competitors for multi-patterning can only be as good as the precision of the masking laid down before each etching step, and it claims that process is prone to imprecision, resulting in lower-quality features and less consistent electrical characteristics in the final chip.
More broadly, Intel is defining its "hyper-scaling" innovations as proprietary technology that will allow it to achieve greater density increases than a pure process shrink alone would. As it moves to 10-nm production, Intel says it'll be using three of these techniques to achieve those "hyper-scaling" gains.
For one, Intel 10-nm FinFET will increase fin height and decrease fin pitch, two improvements that are the hallmarks of higher-performance 3D transistors. 10-nm fin pitch will decrease from 42 nm on the 14-nm process to 34 nm on 10nm, while fin height will grow from 42 nm to 54 nm. To lay down those fins, 10nm will use an industry-standard 193-nm light source paired with another advance in Intel's multi-patterning technology, called self-aligned quad-patterning.
Additionally, this method will allow Intel to achieve a 36-nm interconnect pitch, which it claims is the tightest in the industry.
The logic cell height of Intel 10-nm will also be shrinking compared to 14-nm technologies. A basic logic cell in Intel 14-nm is 399nm tall, while 10-nm will decrease that figure to 272 nm, or a 0.68x reduction.
Aside from the changes in feature sizes, Intel will also be using two new techniques to reduce the area occupied by each logic cell on the chip. The first of these is called contact-over-active-gate technology. In the past, Intel says contacts have had to be laid down beside a transistor. Contact-over-active-gate allows Intel to place these elements directly above the transistor, saving space and increasing density. Intel says the contact-over-active-gate approach allows it to achieve 10% greater logic density in a given area than it would without the tech.
Another change in Intel's move to 10nm is the use of single dummy gates at the edges of its logic cells. Dummy gates are used to isolate logic devices from one another on the chip, and Intel's 14-nm node used two of these features at each edge of each logic cell. Reducing the number of dummy gates per cell from two to one lets the company enjoy 20% greater area scaling compared to its approach at 14nm.
All together, Intel claims the four improvements it's disclosing for its 10-nm process let it achieve a 0.37x reduction in logic area on die compared to its 14-nm process, as well as a 2.7x logic density improvement—well above the 2x scaling that Moore's Law would lead us to expect.
Taken as a whole, a hypothetical Intel chip with logic, I/O, and SRAM circuitry is purported to be 0.43x the size of a similar chip fabricated on Intel 14-nm FinFET.
Using the MTr/mm² metric it introduced yesterday, Intel claims its 10-nm process will deliver an eye-popping 100 MTr/mm² for logic, and it believes its competitors' 10-nm processes will deliver roughly half that density. In remarkably pointed commentary, Intel says that density deficit represents a three-year lead for its own process technology.
Over the life of the 10-nm process, Intel further plans to deliver two refinements to the node that will improve performance, just as it will for its 14-nm tech. For its first round of refinements, the company expects 15% better performance at the same power level, or similar performance for 30% less power.
As we noted earlier, however, the company doesn't expect its 10-nm transistors to meet or exceed the performance of its third-gen 14-nm FinFETs until this first round of refinements, or perhaps even until the second round of refinements. The advantages from 10nm could primarily come from the increase in density and a decrease in power consumption, at least at first.