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Getting Ryzen ready for Raven Ridge
The Ryzen family of APUs are smarter about revving up CPU clocks compared to the Precision Boost behavior in their desktop brethren, thanks to a new per-core boost mechanism called Precision Boost 2.

Much like Intel's Turbo Boost 2.0, AMD describes this new approach as an opportunistic scheme that will extract the maximum possible boost speed from every core given thermal and workload characteristics, using the same 25-MHz granularity available from existing Ryzen chips.

As a result, the "two-core boost" and "all-core boost" figures that AMD has provided for past Ryzen CPUs won't apply to Raven Ridge SoCs or future Ryzen CPUs. Instead, active CPU cores will gracefully throttle up or down as workloads and thermals allow.

Also thanks to the SenseMI suite of technologies in the Zen architecture, AMD's Extended Frequency Range (XFR) technology will be coming to Ryzen APUs as Mobile XFR. Like their desktop counterparts, Raven Ridge parts will be able to boost above their specified maximum boost clocks if a given system's cooling hardware, thermal conditions and workloads allow.

Don't expect to see the same XFR headroom from every system, though—assuming you see it at all. AMD suggests the feature is always active, but it also noted that XFR will only be available in "premium notebooks with great cooling solutions," and it further notes that a product will have to meet the company's own performance criteria in order to ship with mobile XFR enabled. The end notes of AMD's presentation suggest that one of those criteria will be the system with mobile XFR enabled could apparently handle 25W of waste heat from the CPU, so we wouldn't expect to see it in the thinnest and lightest systems with Ryzen APUs inside.

To manage power from the host system, Ryzen APUs will take advantage of integrated low-dropout regulators (LDOs) on board the SoC itself. Voltage regulation on Ryzen desktop CPUs is performed by external circuitry on the motherboard (even though LDOs are present in desktop Zen dies), but the integrated LDOs take center stage in the move to mobile.

AMD claims the combination of a shared voltage rail and regulator from the motherboard, in tandem with the on-die LDOs, allow it to reduce current requirements from the external voltage regulator and to build smaller and lighter laptops. Because each CPU core has its own LDO, as does the IGP, those regulators can also act as fine-grained power gates to let unused elements of the chip power down when they're not needed.

The use of the LDOs on board Raven Ridge also gives AMD full per-core frequency and voltage control for all CPU cores and the integrated GPU based on workload. If only some CPU cores are under heavy load, for example, the chip can direct power and raise clocks where needed while throttling back less-stressed functional units.

These tradeoffs can also happen across the SoC if the graphics processor is under heavy load and the CPU isn't, according to the company. Since all this monitoring and adjustment is occurring on-die, AMD claims that adjustments happen more quickly and accurately than they otherwise might.

When the SoC is largely idle, AMD can employ a range of power-saving techniques. Each core can enter the C6 deep-sleep state when it's idle, and if all cores enter the C6 state for a long enough period, a CPUOFF state reduces the power flowing to the L3 cache, as well. Similarly, the LDOs allow the graphics portion of the die to be power-gated when it's not being used, and a deeper GFXOFF state reduces power to the GPU's uncore. Finally, if both functional units enter deep-sleep states, a VDDOFF state will halt the external voltage regulator. Power-saving schemes like these have been present in past APUs, but this implementation seems to be the most integrated and refined that AMD has shipped so far.

The Infinity Fabric on Raven Ridge is subdivided into two regions whose members share distinct characteristics: those that can remain gated off during display refreshes, and those that need to become active for short periods during those events. AMD's designers worked to separate and minimize components of the fabric that need to be able to become active during display refreshes from those that can remain gated off in order to save more power.

If deep-sleep states are important for power saving, being able to quickly respond to a user's demand for processing power is just as critical. AMD claims that the Raven Ridge SoC is generally able to wake up gated-off components much faster than the Bristol Ridge FX-9800P could, thanks to state saving and restoring optimizations in the Zen pipeline, retention registers in the Vega GPU that reduce the need for saving operations, and a bypass for the phase locked loop clock that prevents that component from slowing the elements of the SoC during wakeup.

A comparatively easier-to-explain change is that the Raven Ridge SoC package itself is only 1.38 mm thick, down from 1.82 mm for similar chips from the Bristol Ridge generation of APUs. Every millimeter counts these days, and paring off even fractions of one will likely help AMD's design partners put Raven Ridge APUs in chassis that one could shave with.